1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform_def.h> 14 #include <platform.h> 15 #include <secure_partition.h> 16 17 extern const mmap_region_t plat_arm_mmap[]; 18 19 /* Weak definitions may be overridden in specific ARM standard platform */ 20 #pragma weak plat_get_ns_image_entrypoint 21 #pragma weak plat_arm_get_mmap 22 23 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 24 * conflicts with the definition in plat/common. */ 25 #if ERROR_DEPRECATED 26 #pragma weak plat_get_syscnt_freq2 27 #endif 28 29 /* 30 * Set up the page tables for the generic and platform-specific memory regions. 31 * The extents of the generic memory regions are specified by the function 32 * arguments and consist of: 33 * - Trusted SRAM seen by the BL image; 34 * - Code section; 35 * - Read-only data section; 36 * - Coherent memory region, if applicable. 37 */ 38 void arm_setup_page_tables(uintptr_t total_base, 39 size_t total_size, 40 uintptr_t code_start, 41 uintptr_t code_limit, 42 uintptr_t rodata_start, 43 uintptr_t rodata_limit 44 #if USE_COHERENT_MEM 45 , 46 uintptr_t coh_start, 47 uintptr_t coh_limit 48 #endif 49 ) 50 { 51 /* 52 * Map the Trusted SRAM with appropriate memory attributes. 53 * Subsequent mappings will adjust the attributes for specific regions. 54 */ 55 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 56 (void *) total_base, (void *) (total_base + total_size)); 57 mmap_add_region(total_base, total_base, 58 total_size, 59 MT_MEMORY | MT_RW | MT_SECURE); 60 61 /* Re-map the code section */ 62 VERBOSE("Code region: %p - %p\n", 63 (void *) code_start, (void *) code_limit); 64 mmap_add_region(code_start, code_start, 65 code_limit - code_start, 66 MT_CODE | MT_SECURE); 67 68 /* Re-map the read-only data section */ 69 VERBOSE("Read-only data region: %p - %p\n", 70 (void *) rodata_start, (void *) rodata_limit); 71 mmap_add_region(rodata_start, rodata_start, 72 rodata_limit - rodata_start, 73 MT_RO_DATA | MT_SECURE); 74 75 #if USE_COHERENT_MEM 76 /* Re-map the coherent memory region */ 77 VERBOSE("Coherent region: %p - %p\n", 78 (void *) coh_start, (void *) coh_limit); 79 mmap_add_region(coh_start, coh_start, 80 coh_limit - coh_start, 81 MT_DEVICE | MT_RW | MT_SECURE); 82 #endif 83 84 #if ENABLE_SPM && defined(IMAGE_BL31) 85 /* The address of the following region is calculated by the linker. */ 86 mmap_add_region(SP_IMAGE_XLAT_TABLES_START, 87 SP_IMAGE_XLAT_TABLES_START, 88 SP_IMAGE_XLAT_TABLES_SIZE, 89 MT_MEMORY | MT_RW | MT_SECURE); 90 #endif 91 92 /* Now (re-)map the platform-specific memory regions */ 93 mmap_add(plat_arm_get_mmap()); 94 95 /* Create the page tables to reflect the above mappings */ 96 init_xlat_tables(); 97 } 98 99 uintptr_t plat_get_ns_image_entrypoint(void) 100 { 101 #ifdef PRELOADED_BL33_BASE 102 return PRELOADED_BL33_BASE; 103 #else 104 return PLAT_ARM_NS_IMAGE_OFFSET; 105 #endif 106 } 107 108 /******************************************************************************* 109 * Gets SPSR for BL32 entry 110 ******************************************************************************/ 111 uint32_t arm_get_spsr_for_bl32_entry(void) 112 { 113 /* 114 * The Secure Payload Dispatcher service is responsible for 115 * setting the SPSR prior to entry into the BL32 image. 116 */ 117 return 0; 118 } 119 120 /******************************************************************************* 121 * Gets SPSR for BL33 entry 122 ******************************************************************************/ 123 #ifndef AARCH32 124 uint32_t arm_get_spsr_for_bl33_entry(void) 125 { 126 unsigned int mode; 127 uint32_t spsr; 128 129 /* Figure out what mode we enter the non-secure world in */ 130 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 131 132 /* 133 * TODO: Consider the possibility of specifying the SPSR in 134 * the FIP ToC and allowing the platform to have a say as 135 * well. 136 */ 137 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 138 return spsr; 139 } 140 #else 141 /******************************************************************************* 142 * Gets SPSR for BL33 entry 143 ******************************************************************************/ 144 uint32_t arm_get_spsr_for_bl33_entry(void) 145 { 146 unsigned int hyp_status, mode, spsr; 147 148 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 149 150 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 151 152 /* 153 * TODO: Consider the possibility of specifying the SPSR in 154 * the FIP ToC and allowing the platform to have a say as 155 * well. 156 */ 157 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 158 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 159 return spsr; 160 } 161 #endif /* AARCH32 */ 162 163 /******************************************************************************* 164 * Configures access to the system counter timer module. 165 ******************************************************************************/ 166 #ifdef ARM_SYS_TIMCTL_BASE 167 void arm_configure_sys_timer(void) 168 { 169 unsigned int reg_val; 170 171 #if ARM_CONFIG_CNTACR 172 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 173 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 174 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 175 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 176 #endif /* ARM_CONFIG_CNTACR */ 177 178 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 179 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 180 } 181 #endif /* ARM_SYS_TIMCTL_BASE */ 182 183 /******************************************************************************* 184 * Returns ARM platform specific memory map regions. 185 ******************************************************************************/ 186 const mmap_region_t *plat_arm_get_mmap(void) 187 { 188 return plat_arm_mmap; 189 } 190 191 #ifdef ARM_SYS_CNTCTL_BASE 192 193 unsigned int plat_get_syscnt_freq2(void) 194 { 195 unsigned int counter_base_frequency; 196 197 /* Read the frequency from Frequency modes table */ 198 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 199 200 /* The first entry of the frequency modes table must not be 0 */ 201 if (counter_base_frequency == 0) 202 panic(); 203 204 return counter_base_frequency; 205 } 206 207 #endif /* ARM_SYS_CNTCTL_BASE */ 208 209 #if SDEI_SUPPORT 210 /* 211 * Translate SDEI entry point to PA, and perform standard ARM entry point 212 * validation on it. 213 */ 214 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 215 { 216 uint64_t par, pa; 217 uint32_t scr_el3; 218 219 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 220 scr_el3 = read_scr_el3(); 221 write_scr_el3(scr_el3 | SCR_NS_BIT); 222 isb(); 223 224 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 225 if (client_mode == MODE_EL2) { 226 /* 227 * Translate entry point to Physical Address using the EL2 228 * translation regime. 229 */ 230 ats1e2r(ep); 231 } else { 232 /* 233 * Translate entry point to Physical Address using the EL1&0 234 * translation regime, including stage 2. 235 */ 236 ats12e1r(ep); 237 } 238 isb(); 239 par = read_par_el1(); 240 241 /* Restore original SCRL_EL3 */ 242 write_scr_el3(scr_el3); 243 isb(); 244 245 /* If the translation resulted in fault, return failure */ 246 if ((par & PAR_F_MASK) != 0) 247 return -1; 248 249 /* Extract Physical Address from PAR */ 250 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 251 252 /* Perform NS entry point validation on the physical address */ 253 return arm_validate_ns_entrypoint(pa); 254 } 255 #endif 256