1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <drivers/arm/sp805.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/common/platform.h> 18 19 #include <arm_def.h> 20 #include <plat_arm.h> 21 22 /* Weak definitions may be overridden in specific ARM standard platform */ 23 #pragma weak bl1_early_platform_setup 24 #pragma weak bl1_plat_arch_setup 25 #pragma weak bl1_platform_setup 26 #pragma weak bl1_plat_sec_mem_layout 27 #pragma weak bl1_plat_prepare_exit 28 #pragma weak bl1_plat_get_next_image_id 29 #pragma weak plat_arm_bl1_fwu_needed 30 31 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 32 bl1_tzram_layout.total_base, \ 33 bl1_tzram_layout.total_size, \ 34 MT_MEMORY | MT_RW | MT_SECURE) 35 /* 36 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 37 * otherwise one region is defined containing both 38 */ 39 #if SEPARATE_CODE_AND_RODATA 40 #define MAP_BL1_RO MAP_REGION_FLAT( \ 41 BL_CODE_BASE, \ 42 BL1_CODE_END - BL_CODE_BASE, \ 43 MT_CODE | MT_SECURE), \ 44 MAP_REGION_FLAT( \ 45 BL1_RO_DATA_BASE, \ 46 BL1_RO_DATA_END \ 47 - BL_RO_DATA_BASE, \ 48 MT_RO_DATA | MT_SECURE) 49 #else 50 #define MAP_BL1_RO MAP_REGION_FLAT( \ 51 BL_CODE_BASE, \ 52 BL1_CODE_END - BL_CODE_BASE, \ 53 MT_CODE | MT_SECURE) 54 #endif 55 56 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 57 static meminfo_t bl1_tzram_layout; 58 59 struct meminfo *bl1_plat_sec_mem_layout(void) 60 { 61 return &bl1_tzram_layout; 62 } 63 64 /******************************************************************************* 65 * BL1 specific platform actions shared between ARM standard platforms. 66 ******************************************************************************/ 67 void arm_bl1_early_platform_setup(void) 68 { 69 70 #if !ARM_DISABLE_TRUSTED_WDOG 71 /* Enable watchdog */ 72 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 73 #endif 74 75 /* Initialize the console to provide early debug support */ 76 arm_console_boot_init(); 77 78 /* Allow BL1 to see the whole Trusted RAM */ 79 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 80 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 81 } 82 83 void bl1_early_platform_setup(void) 84 { 85 arm_bl1_early_platform_setup(); 86 87 /* 88 * Initialize Interconnect for this cluster during cold boot. 89 * No need for locks as no other CPU is active. 90 */ 91 plat_arm_interconnect_init(); 92 /* 93 * Enable Interconnect coherency for the primary CPU's cluster. 94 */ 95 plat_arm_interconnect_enter_coherency(); 96 } 97 98 /****************************************************************************** 99 * Perform the very early platform specific architecture setup shared between 100 * ARM standard platforms. This only does basic initialization. Later 101 * architectural setup (bl1_arch_setup()) does not do anything platform 102 * specific. 103 *****************************************************************************/ 104 void arm_bl1_plat_arch_setup(void) 105 { 106 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 107 /* 108 * Ensure ARM platforms don't use coherent memory in BL1 unless 109 * cryptocell integration is enabled. 110 */ 111 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 112 #endif 113 114 const mmap_region_t bl_regions[] = { 115 MAP_BL1_TOTAL, 116 MAP_BL1_RO, 117 #if USE_ROMLIB 118 ARM_MAP_ROMLIB_CODE, 119 ARM_MAP_ROMLIB_DATA, 120 #endif 121 #if ARM_CRYPTOCELL_INTEG 122 ARM_MAP_BL_COHERENT_RAM, 123 #endif 124 {0} 125 }; 126 127 setup_page_tables(bl_regions, plat_arm_get_mmap()); 128 #ifdef AARCH32 129 enable_mmu_svc_mon(0); 130 #else 131 enable_mmu_el3(0); 132 #endif /* AARCH32 */ 133 134 arm_setup_romlib(); 135 } 136 137 void bl1_plat_arch_setup(void) 138 { 139 arm_bl1_plat_arch_setup(); 140 } 141 142 /* 143 * Perform the platform specific architecture setup shared between 144 * ARM standard platforms. 145 */ 146 void arm_bl1_platform_setup(void) 147 { 148 /* Initialise the IO layer and register platform IO devices */ 149 plat_arm_io_setup(); 150 arm_load_tb_fw_config(); 151 #if TRUSTED_BOARD_BOOT 152 /* Share the Mbed TLS heap info with other images */ 153 arm_bl1_set_mbedtls_heap(); 154 #endif /* TRUSTED_BOARD_BOOT */ 155 156 /* 157 * Allow access to the System counter timer module and program 158 * counter frequency for non secure images during FWU 159 */ 160 arm_configure_sys_timer(); 161 write_cntfrq_el0(plat_get_syscnt_freq2()); 162 } 163 164 void bl1_platform_setup(void) 165 { 166 arm_bl1_platform_setup(); 167 } 168 169 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 170 { 171 #if !ARM_DISABLE_TRUSTED_WDOG 172 /* Disable watchdog before leaving BL1 */ 173 sp805_stop(ARM_SP805_TWDG_BASE); 174 #endif 175 176 #ifdef EL3_PAYLOAD_BASE 177 /* 178 * Program the EL3 payload's entry point address into the CPUs mailbox 179 * in order to release secondary CPUs from their holding pen and make 180 * them jump there. 181 */ 182 plat_arm_program_trusted_mailbox(ep_info->pc); 183 dsbsy(); 184 sev(); 185 #endif 186 } 187 188 /* 189 * On Arm platforms, the FWU process is triggered when the FIP image has 190 * been tampered with. 191 */ 192 int plat_arm_bl1_fwu_needed(void) 193 { 194 return (arm_io_is_toc_valid() != 1); 195 } 196 197 /******************************************************************************* 198 * The following function checks if Firmware update is needed, 199 * by checking if TOC in FIP image is valid or not. 200 ******************************************************************************/ 201 unsigned int bl1_plat_get_next_image_id(void) 202 { 203 if (plat_arm_bl1_fwu_needed() != 0) 204 return NS_BL1U_IMAGE_ID; 205 206 return BL2_IMAGE_ID; 207 } 208