| 47b83ad2 | 28-Dec-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Passing EKS size as boot arg to trusty
* EKS blob size was not passed by as a boot parameter
earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
update the boot pa
Tegra: Passing EKS size as boot arg to trusty
* EKS blob size was not passed by as a boot parameter
earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
update the boot parameter from default value to the argument
passed by bootloader
Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098
Signed-off-by: Akshay Sharan <asharan@nvidia.com>
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| 8668fe0c | 15-May-2017 |
Sam Payne <spayne@nvidia.com> |
Tegra210B01: initialize DRBG on boot and resume
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume fo
Tegra210B01: initialize DRBG on boot and resume
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume for SE1 and SE2. This SRK
value is not saved to PMC scratch, and should be overwitten
during atomic suspend.
Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c
Signed-off-by: Sam Payne <spayne@nvidia.com>
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| dd1a71f1 | 05-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra210: bpmp: power management interface
This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power sta
Tegra210: bpmp: power management interface
This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.
Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a9cd8630 | 08-May-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra186: mce: fix trivial MISRA defects
This patch fixes MISRA defects for the MCE driver.
* Using logical NOT for bool type function
* Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace
MPI
Tegra186: mce: fix trivial MISRA defects
This patch fixes MISRA defects for the MCE driver.
* Using logical NOT for bool type function
* Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace
MPIDR_CLUSTER_MASK
Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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| 7aba390f | 08-May-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: A
Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 82e73ae7 | 08-May-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: fiq_glue: fix MISRA defects for Rule 2.7
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Sig
Tegra: fiq_glue: fix MISRA defects for Rule 2.7
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| ce3c97c9 | 11-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.
Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 1d49112b | 01-Mar-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 322e7c3e | 10-Apr-2017 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, where
Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d3b71331 | 12-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra: platform: helper functions to read chip ID
This patch adds helper functions to find out the chip ID of the
Tegra SoC.
Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marv
Tegra: platform: helper functions to read chip ID
This patch adds helper functions to find out the chip ID of the
Tegra SoC.
Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 0a2d5b43 | 02-Feb-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
types: use int-ll64 for both aarch32 and aarch64
Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch
types: use int-ll64 for both aarch32 and aarch64
Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch32 and aarch64.
For example, uint64_t is defined as 'unsigned long long' for aarch32
and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined
as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64.
A problem typically arises when you use printf() in common code.
One solution could be, to cast the arguments to a type long enough
for both architectures. For example, if 'val' is uint64_t type,
like this:
printf("val = %llx\n", (unsigned long long)val);
Or, somebody may suggest to use a macro provided by <inttypes.h>,
like this:
printf("val = %" PRIx64 "\n", val);
But, both would make the code ugly.
The solution adopted in Linux kernel is to use the same typedefs for
all architectures. The fixed integer types in the kernel-space have
been unified into int-ll64, like follows:
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef signed short int16_t;
typedef unsigned short uint16_t;
typedef signed int int32_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
[ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ]
This gets along with the codebase shared between 32 bit and 64 bit,
with the data model called ILP32, LP64, respectively.
The width for primitive types is defined as follows:
ILP32 LP64
int 32 32
long 32 64
long long 64 64
pointer 32 64
'long long' is 64 bit for both, so it is used for defining uint64_t.
'long' has the same width as pointer, so for uintptr_t.
We still need an ifdef conditional for (s)size_t.
All 64 bit architectures use "unsigned long" size_t, and most 32 bit
architectures use "unsigned int" size_t. H8/300, S/390 are known as
exceptions; they use "unsigned long" size_t despite their architecture
is 32 bit.
One idea for simplification might be to define size_t as 'unsigned long'
across architectures, then forbid the use of "%z" string format.
However, this would cause a distortion between size_t and sizeof()
operator. We have unknowledge about the native type of sizeof(), so
we need a guess of it anyway. I want the following formula to always
return 1:
__builtin_types_compatible_p(size_t, typeof(sizeof(int)))
Fortunately, ARM is probably a majority case. As far as I know, all
32 bit ARM compilers use "unsigned int" size_t.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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