1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SE_PRIVATE_H 9 #define SE_PRIVATE_H 10 11 #include <stdbool.h> 12 #include <security_engine.h> 13 14 /* 15 * PMC registers 16 */ 17 18 /* Secure scratch registers */ 19 #define PMC_SECURE_SCRATCH4_OFFSET 0xC0U 20 #define PMC_SECURE_SCRATCH5_OFFSET 0xC4U 21 #define PMC_SECURE_SCRATCH6_OFFSET 0x224U 22 #define PMC_SECURE_SCRATCH7_OFFSET 0x228U 23 #define PMC_SECURE_SCRATCH120_OFFSET 0xB38U 24 #define PMC_SECURE_SCRATCH121_OFFSET 0xB3CU 25 #define PMC_SECURE_SCRATCH122_OFFSET 0xB40U 26 #define PMC_SECURE_SCRATCH123_OFFSET 0xB44U 27 28 /* 29 * AHB arbitration memory write queue 30 */ 31 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU 32 #define ARAHB_MST_ID_SE2_MASK (0x1U << 13) 33 #define ARAHB_MST_ID_SE_MASK (0x1U << 14) 34 35 /* SE Status register */ 36 #define SE_STATUS_OFFSET 0x800U 37 #define SE_STATUS_SHIFT 0 38 #define SE_STATUS_IDLE \ 39 ((0U) << SE_STATUS_SHIFT) 40 #define SE_STATUS_BUSY \ 41 ((1U) << SE_STATUS_SHIFT) 42 #define SE_STATUS(x) \ 43 ((x) & ((0x3U) << SE_STATUS_SHIFT)) 44 45 /* SE config register */ 46 #define SE_CONFIG_REG_OFFSET 0x14U 47 #define SE_CONFIG_ENC_ALG_SHIFT 12 48 #define SE_CONFIG_ENC_ALG_AES_ENC \ 49 ((1U) << SE_CONFIG_ENC_ALG_SHIFT) 50 #define SE_CONFIG_ENC_ALG_RNG \ 51 ((2U) << SE_CONFIG_ENC_ALG_SHIFT) 52 #define SE_CONFIG_ENC_ALG_SHA \ 53 ((3U) << SE_CONFIG_ENC_ALG_SHIFT) 54 #define SE_CONFIG_ENC_ALG_RSA \ 55 ((4U) << SE_CONFIG_ENC_ALG_SHIFT) 56 #define SE_CONFIG_ENC_ALG_NOP \ 57 ((0U) << SE_CONFIG_ENC_ALG_SHIFT) 58 #define SE_CONFIG_ENC_ALG(x) \ 59 ((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT)) 60 61 #define SE_CONFIG_DEC_ALG_SHIFT 8 62 #define SE_CONFIG_DEC_ALG_AES \ 63 ((1U) << SE_CONFIG_DEC_ALG_SHIFT) 64 #define SE_CONFIG_DEC_ALG_NOP \ 65 ((0U) << SE_CONFIG_DEC_ALG_SHIFT) 66 #define SE_CONFIG_DEC_ALG(x) \ 67 ((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT)) 68 69 #define SE_CONFIG_DST_SHIFT 2 70 #define SE_CONFIG_DST_MEMORY \ 71 ((0U) << SE_CONFIG_DST_SHIFT) 72 #define SE_CONFIG_DST_HASHREG \ 73 ((1U) << SE_CONFIG_DST_SHIFT) 74 #define SE_CONFIG_DST_KEYTAB \ 75 ((2U) << SE_CONFIG_DST_SHIFT) 76 #define SE_CONFIG_DST_SRK \ 77 ((3U) << SE_CONFIG_DST_SHIFT) 78 #define SE_CONFIG_DST_RSAREG \ 79 ((4U) << SE_CONFIG_DST_SHIFT) 80 #define SE_CONFIG_DST(x) \ 81 ((x) & ((0x7U) << SE_CONFIG_DST_SHIFT)) 82 83 /* DRNG random number generator config */ 84 #define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U 85 86 #define DRBG_RO_ENT_SRC_SHIFT 1 87 #define DRBG_RO_ENT_SRC_ENABLE \ 88 ((1U) << DRBG_RO_ENT_SRC_SHIFT) 89 #define DRBG_RO_ENT_SRC_DISABLE \ 90 ((0U) << DRBG_RO_ENT_SRC_SHIFT) 91 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) \ 92 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_SHIFT)) 93 94 #define DRBG_RO_ENT_SRC_LOCK_SHIFT 0 95 #define DRBG_RO_ENT_SRC_LOCK_ENABLE \ 96 ((1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 97 #define DRBG_RO_ENT_SRC_LOCK_DISABLE \ 98 ((0U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 99 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) \ 100 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)) 101 102 #define DRBG_RO_ENT_IGNORE_MEM_SHIFT 12 103 #define DRBG_RO_ENT_IGNORE_MEM_ENABLE \ 104 ((1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 105 #define DRBG_RO_ENT_IGNORE_MEM_DISABLE \ 106 ((0U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 107 #define SE_RNG_SRC_CONFIG_RO_ENT_IGNORE_MEM(x) \ 108 ((x) & ((0x1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)) 109 110 /* SE OPERATION */ 111 #define SE_OPERATION_REG_OFFSET 0x8U 112 #define SE_OPERATION_SHIFT 0 113 #define SE_OP_ABORT \ 114 ((0x0U) << SE_OPERATION_SHIFT) 115 #define SE_OP_START \ 116 ((0x1U) << SE_OPERATION_SHIFT) 117 #define SE_OP_RESTART \ 118 ((0x2U) << SE_OPERATION_SHIFT) 119 #define SE_OP_CTX_SAVE \ 120 ((0x3U) << SE_OPERATION_SHIFT) 121 #define SE_OP_RESTART_IN \ 122 ((0x4U) << SE_OPERATION_SHIFT) 123 #define SE_OPERATION(x) \ 124 ((x) & ((0x7U) << SE_OPERATION_SHIFT)) 125 126 /* SE_CTX_SAVE_AUTO */ 127 #define SE_CTX_SAVE_AUTO_REG_OFFSET 0x74U 128 129 /* Enable */ 130 #define SE_CTX_SAVE_AUTO_ENABLE_SHIFT 0 131 #define SE_CTX_SAVE_AUTO_DIS \ 132 ((0U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 133 #define SE_CTX_SAVE_AUTO_EN \ 134 ((1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 135 #define SE_CTX_SAVE_AUTO_ENABLE(x) \ 136 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)) 137 138 /* Lock */ 139 #define SE_CTX_SAVE_AUTO_LOCK_SHIFT 8 140 #define SE_CTX_SAVE_AUTO_LOCK_EN \ 141 ((1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 142 #define SE_CTX_SAVE_AUTO_LOCK_DIS \ 143 ((0U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 144 #define SE_CTX_SAVE_AUTO_LOCK(x) \ 145 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)) 146 147 /* Current context save number of blocks */ 148 #define SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT 16 149 #define SE_CTX_SAVE_AUTO_CURR_CNT_MASK 0x3FFU 150 #define SE_CTX_SAVE_GET_BLK_COUNT(x) \ 151 (((x) >> SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT) & \ 152 SE_CTX_SAVE_AUTO_CURR_CNT_MASK) 153 154 #define SE_CTX_SAVE_SIZE_BLOCKS_SE1 133 155 #define SE_CTX_SAVE_SIZE_BLOCKS_SE2 646 156 157 /* SE TZRAM OPERATION - only for SE1 */ 158 #define SE_TZRAM_OPERATION 0x540U 159 160 #define SE_TZRAM_OP_MODE_SHIFT 1 161 #define SE_TZRAM_OP_MODE_SAVE \ 162 ((0U) << SE_TZRAM_OP_MODE_SHIFT) 163 #define SE_TZRAM_OP_MODE_RESTORE \ 164 ((1U) << SE_TZRAM_OP_MODE_SHIFT) 165 #define SE_TZRAM_OP_MODE(x) \ 166 ((x) & ((0x1U) << SE_TZRAM_OP_MODE_SHIFT)) 167 168 #define SE_TZRAM_OP_BUSY_SHIFT 2 169 #define SE_TZRAM_OP_BUSY_OFF \ 170 ((0U) << SE_TZRAM_OP_BUSY_SHIFT) 171 #define SE_TZRAM_OP_BUSY_ON \ 172 ((1U) << SE_TZRAM_OP_BUSY_SHIFT) 173 #define SE_TZRAM_OP_BUSY(x) \ 174 ((x) & ((0x1U) << SE_TZRAM_OP_BUSY_SHIFT)) 175 176 #define SE_TZRAM_OP_REQ_SHIFT 0 177 #define SE_TZRAM_OP_REQ_IDLE \ 178 ((0U) << SE_TZRAM_OP_REQ_SHIFT) 179 #define SE_TZRAM_OP_REQ_INIT \ 180 ((1U) << SE_TZRAM_OP_REQ_SHIFT) 181 #define SE_TZRAM_OP_REQ(x) \ 182 ((x) & ((0x1U) << SE_TZRAM_OP_REQ_SHIFT)) 183 184 /* SE Interrupt */ 185 #define SE_INT_STATUS_REG_OFFSET 0x10U 186 #define SE_INT_OP_DONE_SHIFT 4 187 #define SE_INT_OP_DONE_CLEAR \ 188 ((0U) << SE_INT_OP_DONE_SHIFT) 189 #define SE_INT_OP_DONE_ACTIVE \ 190 ((1U) << SE_INT_OP_DONE_SHIFT) 191 #define SE_INT_OP_DONE(x) \ 192 ((x) & ((0x1U) << SE_INT_OP_DONE_SHIFT)) 193 194 /* SE error status */ 195 #define SE_ERR_STATUS_REG_OFFSET 0x804U 196 197 /* SE linked list (LL) register */ 198 #define SE_IN_LL_ADDR_REG_OFFSET 0x18U 199 #define SE_OUT_LL_ADDR_REG_OFFSET 0x24U 200 #define SE_BLOCK_COUNT_REG_OFFSET 0x318U 201 202 /* AES data sizes */ 203 #define TEGRA_SE_AES_BLOCK_SIZE 16 204 #define TEGRA_SE_AES_MIN_KEY_SIZE 16 205 #define TEGRA_SE_AES_MAX_KEY_SIZE 32 206 #define TEGRA_SE_AES_IV_SIZE 16 207 208 /******************************************************************************* 209 * Inline functions definition 210 ******************************************************************************/ 211 212 static inline uint32_t tegra_se_read_32(const tegra_se_dev_t *dev, uint32_t offset) 213 { 214 return mmio_read_32(dev->se_base + offset); 215 } 216 217 static inline void tegra_se_write_32(const tegra_se_dev_t *dev, uint32_t offset, uint32_t val) 218 { 219 mmio_write_32(dev->se_base + offset, val); 220 } 221 222 /******************************************************************************* 223 * Prototypes 224 ******************************************************************************/ 225 226 #endif /* SE_PRIVATE_H */ 227