1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/common/platform.h> 17 18 #include <flowctrl.h> 19 #include <pmc.h> 20 #include <tegra_def.h> 21 #include <tegra_private.h> 22 #include <tegra_platform.h> 23 #include <security_engine.h> 24 25 /* 26 * Register used to clear CPU reset signals. Each CPU has two reset 27 * signals: CPU reset (3:0) and Core reset (19:16). 28 */ 29 #define CPU_CMPLX_RESET_CLR 0x454 30 #define CPU_CORE_RESET_MASK 0x10001 31 32 /* Clock and Reset controller registers for system clock's settings */ 33 #define SCLK_RATE 0x30 34 #define SCLK_BURST_POLICY 0x28 35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 36 37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 38 39 int32_t tegra_soc_validate_power_state(unsigned int power_state, 40 psci_power_state_t *req_state) 41 { 42 int state_id = psci_get_pstate_id(power_state); 43 44 /* Sanity check the requested state id */ 45 switch (state_id) { 46 case PSTATE_ID_CORE_POWERDN: 47 /* 48 * Core powerdown request only for afflvl 0 49 */ 50 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 51 52 break; 53 54 case PSTATE_ID_CLUSTER_IDLE: 55 case PSTATE_ID_CLUSTER_POWERDN: 56 /* 57 * Cluster powerdown/idle request only for afflvl 1 58 */ 59 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 60 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 61 62 break; 63 64 case PSTATE_ID_SOC_POWERDN: 65 /* 66 * System powerdown request only for afflvl 2 67 */ 68 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 69 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 70 71 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 72 PLAT_SYS_SUSPEND_STATE_ID; 73 74 break; 75 76 default: 77 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 78 return PSCI_E_INVALID_PARAMS; 79 } 80 81 return PSCI_E_SUCCESS; 82 } 83 84 /******************************************************************************* 85 * Platform handler to calculate the proper target power level at the 86 * specified affinity level 87 ******************************************************************************/ 88 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 89 const plat_local_state_t *states, 90 unsigned int ncpu) 91 { 92 plat_local_state_t target = *states; 93 int cpu = plat_my_core_pos(); 94 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 95 96 /* get the power state at this level */ 97 if (lvl == MPIDR_AFFLVL1) 98 target = *(states + core_pos); 99 if (lvl == MPIDR_AFFLVL2) 100 target = *(states + cpu); 101 102 /* Cluster idle/power-down */ 103 if ((lvl == MPIDR_AFFLVL1) && ((target == PSTATE_ID_CLUSTER_IDLE) || 104 (target == PSTATE_ID_CLUSTER_POWERDN))) { 105 return target; 106 } 107 108 /* System Suspend */ 109 if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 110 (target == PSTATE_ID_SOC_POWERDN)) 111 return PSTATE_ID_SOC_POWERDN; 112 113 /* default state */ 114 return PSCI_LOCAL_STATE_RUN; 115 } 116 117 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 118 { 119 u_register_t mpidr = read_mpidr(); 120 const plat_local_state_t *pwr_domain_state = 121 target_state->pwr_domain_state; 122 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 123 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 124 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 125 int ret = PSCI_E_SUCCESS; 126 127 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 128 129 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 130 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 131 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 132 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 133 134 if (tegra_chipid_is_t210_b01()) { 135 /* Suspend se/se2 and pka1 */ 136 if (tegra_se_suspend() != 0) { 137 ret = PSCI_E_INTERN_FAIL; 138 } 139 140 /* Save tzram contents */ 141 if (tegra_se_save_tzram() != 0) { 142 ret = PSCI_E_INTERN_FAIL; 143 } 144 } 145 146 /* suspend the entire soc */ 147 if (ret == PSCI_E_SUCCESS) { 148 tegra_fc_soc_powerdn(mpidr); 149 } 150 151 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 152 153 assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_IDLE); 154 155 /* Prepare for cluster idle */ 156 tegra_fc_cluster_idle(mpidr); 157 158 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 159 160 assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_POWERDN); 161 162 /* Prepare for cluster powerdn */ 163 tegra_fc_cluster_powerdn(mpidr); 164 165 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 166 167 /* Prepare for cpu powerdn */ 168 tegra_fc_cpu_powerdn(mpidr); 169 170 } else { 171 ERROR("%s: Unknown state id\n", __func__); 172 ret = PSCI_E_NOT_SUPPORTED; 173 } 174 175 return ret; 176 } 177 178 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 179 { 180 uint32_t val; 181 182 /* 183 * Check if we are exiting from SOC_POWERDN. 184 */ 185 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 186 PLAT_SYS_SUSPEND_STATE_ID) { 187 188 /* 189 * Security engine resume 190 */ 191 if (tegra_chipid_is_t210_b01()) { 192 tegra_se_resume(); 193 } 194 195 /* 196 * Lock scratch registers which hold the CPU vectors 197 */ 198 tegra_pmc_lock_cpu_vectors(); 199 200 /* 201 * Enable WRAP to INCR burst type conversions for 202 * incoming requests on the AXI slave ports. 203 */ 204 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 205 val &= ~ENABLE_UNSUP_TX_ERRORS; 206 val |= ENABLE_WRAP_TO_INCR_BURSTS; 207 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 208 209 /* 210 * Restore Boot and Power Management Processor (BPMP) reset 211 * address and reset it. 212 */ 213 tegra_fc_reset_bpmp(); 214 } 215 216 /* 217 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 218 * used for power management and boot purposes. Inform the BPMP that 219 * we have completed the cluster power up. 220 */ 221 tegra_fc_lock_active_cluster(); 222 223 return PSCI_E_SUCCESS; 224 } 225 226 int tegra_soc_pwr_domain_on(u_register_t mpidr) 227 { 228 int cpu = mpidr & MPIDR_CPU_MASK; 229 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 230 231 /* Deassert CPU reset signals */ 232 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 233 234 /* Turn on CPU using flow controller or PMC */ 235 if (cpu_powergate_mask[cpu] == 0) { 236 tegra_pmc_cpu_on(cpu); 237 cpu_powergate_mask[cpu] = 1; 238 } else { 239 tegra_fc_cpu_on(cpu); 240 } 241 242 return PSCI_E_SUCCESS; 243 } 244 245 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 246 { 247 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 248 return PSCI_E_SUCCESS; 249 } 250 251 int tegra_soc_prepare_system_reset(void) 252 { 253 /* 254 * Set System Clock (SCLK) to POR default so that the clock source 255 * for the PMC APB clock would not be changed due to system reset. 256 */ 257 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 258 SCLK_BURST_POLICY_DEFAULT); 259 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 260 261 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 262 mdelay(1); 263 264 return PSCI_E_SUCCESS; 265 } 266