1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <lib/mmio.h> 10 #include <tegra_def.h> 11 #include <tegra_platform.h> 12 #include <tegra_private.h> 13 #include <utils_def.h> 14 15 /******************************************************************************* 16 * Tegra platforms 17 ******************************************************************************/ 18 typedef enum tegra_platform { 19 TEGRA_PLATFORM_SILICON = 0, 20 TEGRA_PLATFORM_QT, 21 TEGRA_PLATFORM_FPGA, 22 TEGRA_PLATFORM_EMULATION, 23 TEGRA_PLATFORM_LINSIM, 24 TEGRA_PLATFORM_UNIT_FPGA, 25 TEGRA_PLATFORM_VIRT_DEV_KIT, 26 TEGRA_PLATFORM_MAX, 27 } tegra_platform_t; 28 29 /******************************************************************************* 30 * Tegra macros defining all the SoC minor versions 31 ******************************************************************************/ 32 #define TEGRA_MINOR_QT U(0) 33 #define TEGRA_MINOR_FPGA U(1) 34 #define TEGRA_MINOR_ASIM_QT U(2) 35 #define TEGRA_MINOR_ASIM_LINSIM U(3) 36 #define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4) 37 #define TEGRA_MINOR_UNIT_FPGA U(5) 38 #define TEGRA_MINOR_VIRT_DEV_KIT U(6) 39 40 /******************************************************************************* 41 * Tegra major, minor version helper macros 42 ******************************************************************************/ 43 #define MAJOR_VERSION_SHIFT U(0x4) 44 #define MAJOR_VERSION_MASK U(0xF) 45 #define MINOR_VERSION_SHIFT U(0x10) 46 #define MINOR_VERSION_MASK U(0xF) 47 #define CHIP_ID_SHIFT U(8) 48 #define CHIP_ID_MASK U(0xFF) 49 #define PRE_SI_PLATFORM_SHIFT U(0x14) 50 #define PRE_SI_PLATFORM_MASK U(0xF) 51 52 /******************************************************************************* 53 * Tegra macros defining all the SoC pre_si_platform 54 ******************************************************************************/ 55 #define TEGRA_PRE_SI_QT U(1) 56 #define TEGRA_PRE_SI_FPGA U(2) 57 #define TEGRA_PRE_SI_UNIT_FPGA U(3) 58 #define TEGRA_PRE_SI_ASIM_QT U(4) 59 #define TEGRA_PRE_SI_ASIM_LINSIM U(5) 60 #define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6) 61 #define TEGRA_PRE_SI_VDK U(8) 62 63 /******************************************************************************* 64 * Tegra chip ID values 65 ******************************************************************************/ 66 typedef enum tegra_chipid { 67 TEGRA_CHIPID_TEGRA13 = 0x13, 68 TEGRA_CHIPID_TEGRA21 = 0x21, 69 TEGRA_CHIPID_TEGRA18 = 0x18, 70 } tegra_chipid_t; 71 72 /* 73 * Read the chip ID value 74 */ 75 static uint32_t tegra_get_chipid(void) 76 { 77 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); 78 } 79 80 /* 81 * Read the chip's major version from chip ID value 82 */ 83 uint32_t tegra_get_chipid_major(void) 84 { 85 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 86 } 87 88 /* 89 * Read the chip's minor version from the chip ID value 90 */ 91 uint32_t tegra_get_chipid_minor(void) 92 { 93 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 94 } 95 96 uint8_t tegra_chipid_is_t132(void) 97 { 98 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 99 100 return (chip_id == TEGRA_CHIPID_TEGRA13); 101 } 102 103 uint8_t tegra_chipid_is_t210(void) 104 { 105 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 106 107 return (chip_id == TEGRA_CHIPID_TEGRA21); 108 } 109 110 uint8_t tegra_chipid_is_t186(void) 111 { 112 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; 113 114 return (chip_id == TEGRA_CHIPID_TEGRA18); 115 } 116 117 /* 118 * Read the chip's pre_si_platform valus from the chip ID value 119 */ 120 static uint32_t tegra_get_chipid_pre_si_platform(void) 121 { 122 return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK; 123 } 124 125 /* 126 * Read the chip ID value and derive the platform 127 */ 128 static tegra_platform_t tegra_get_platform(void) 129 { 130 uint32_t major, minor, pre_si_platform; 131 tegra_platform_t ret; 132 133 /* get the major/minor chip ID values */ 134 major = tegra_get_chipid_major(); 135 minor = tegra_get_chipid_minor(); 136 pre_si_platform = tegra_get_chipid_pre_si_platform(); 137 138 if (major == 0U) { 139 /* 140 * The minor version number is used by simulation platforms 141 */ 142 switch (minor) { 143 /* 144 * Cadence's QuickTurn emulation system is a Solaris-based 145 * chip emulation system 146 */ 147 case TEGRA_MINOR_QT: 148 case TEGRA_MINOR_ASIM_QT: 149 ret = TEGRA_PLATFORM_QT; 150 break; 151 152 /* 153 * FPGAs are used during early software/hardware development 154 */ 155 case TEGRA_MINOR_FPGA: 156 ret = TEGRA_PLATFORM_FPGA; 157 break; 158 /* 159 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 160 * simulation framework. 161 */ 162 case TEGRA_MINOR_ASIM_LINSIM: 163 case TEGRA_MINOR_DSIM_ASIM_LINSIM: 164 ret = TEGRA_PLATFORM_LINSIM; 165 break; 166 167 /* 168 * Unit FPGAs run the actual hardware block IP on the FPGA with 169 * the other parts of the system using Linsim. 170 */ 171 case TEGRA_MINOR_UNIT_FPGA: 172 ret = TEGRA_PLATFORM_UNIT_FPGA; 173 break; 174 /* 175 * The Virtualizer Development Kit (VDK) is the standard chip 176 * development from Synopsis. 177 */ 178 case TEGRA_MINOR_VIRT_DEV_KIT: 179 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 180 break; 181 default: 182 assert(0); 183 ret = TEGRA_PLATFORM_MAX; 184 break; 185 } 186 187 } else if (pre_si_platform > 0U) { 188 189 switch (pre_si_platform) { 190 /* 191 * Cadence's QuickTurn emulation system is a Solaris-based 192 * chip emulation system 193 */ 194 case TEGRA_PRE_SI_QT: 195 case TEGRA_PRE_SI_ASIM_QT: 196 ret = TEGRA_PLATFORM_QT; 197 break; 198 199 /* 200 * FPGAs are used during early software/hardware development 201 */ 202 case TEGRA_PRE_SI_FPGA: 203 ret = TEGRA_PLATFORM_FPGA; 204 break; 205 /* 206 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel 207 * simulation framework. 208 */ 209 case TEGRA_PRE_SI_ASIM_LINSIM: 210 case TEGRA_PRE_SI_DSIM_ASIM_LINSIM: 211 ret = TEGRA_PLATFORM_LINSIM; 212 break; 213 214 /* 215 * Unit FPGAs run the actual hardware block IP on the FPGA with 216 * the other parts of the system using Linsim. 217 */ 218 case TEGRA_PRE_SI_UNIT_FPGA: 219 ret = TEGRA_PLATFORM_UNIT_FPGA; 220 break; 221 /* 222 * The Virtualizer Development Kit (VDK) is the standard chip 223 * development from Synopsis. 224 */ 225 case TEGRA_PRE_SI_VDK: 226 ret = TEGRA_PLATFORM_VIRT_DEV_KIT; 227 break; 228 229 default: 230 assert(0); 231 ret = TEGRA_PLATFORM_MAX; 232 break; 233 } 234 235 } else { 236 /* Actual silicon platforms have a non-zero major version */ 237 ret = TEGRA_PLATFORM_SILICON; 238 } 239 240 return ret; 241 } 242 243 bool tegra_platform_is_silicon(void) 244 { 245 return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false); 246 } 247 248 bool tegra_platform_is_qt(void) 249 { 250 return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false); 251 } 252 253 bool tegra_platform_is_linsim(void) 254 { 255 tegra_platform_t plat = tegra_get_platform(); 256 257 return (((plat == TEGRA_PLATFORM_LINSIM) || 258 (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false); 259 } 260 261 bool tegra_platform_is_fpga(void) 262 { 263 return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false); 264 } 265 266 bool tegra_platform_is_emulation(void) 267 { 268 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); 269 } 270 271 bool tegra_platform_is_unit_fpga(void) 272 { 273 return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false); 274 } 275 276 bool tegra_platform_is_virt_dev_kit(void) 277 { 278 return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false); 279 } 280