1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/bl_common.h> 9 #include <drivers/console.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <platform.h> 12 #include <security_engine.h> 13 #include <tegra_def.h> 14 #include <tegra_platform.h> 15 #include <tegra_private.h> 16 17 /* sets of MMIO ranges setup */ 18 #define MMIO_RANGE_0_ADDR 0x50000000 19 #define MMIO_RANGE_1_ADDR 0x60000000 20 #define MMIO_RANGE_2_ADDR 0x70000000 21 #define MMIO_RANGE_SIZE 0x200000 22 23 /* 24 * Table of regions to map using the MMU. 25 */ 26 static const mmap_region_t tegra_mmap[] = { 27 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 30 MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 {0} 34 }; 35 36 /******************************************************************************* 37 * Set up the pagetables as per the platform memory map & initialize the MMU 38 ******************************************************************************/ 39 const mmap_region_t *plat_get_mmio_map(void) 40 { 41 /* Add the map region for security engine SE2 */ 42 if (tegra_chipid_is_t210_b01()) { 43 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 44 (uint64_t)TEGRA_SE2_BASE, 45 (uint64_t)TEGRA_SE2_RANGE_SIZE, 46 MT_DEVICE | MT_RW | MT_SECURE); 47 } 48 49 /* MMIO space */ 50 return tegra_mmap; 51 } 52 53 /******************************************************************************* 54 * The Tegra power domain tree has a single system level power domain i.e. a 55 * single root node. The first entry in the power domain descriptor specifies 56 * the number of power domains at the highest power level. 57 ******************************************************************************* 58 */ 59 const unsigned char tegra_power_domain_tree_desc[] = { 60 /* No of root nodes */ 61 1, 62 /* No of clusters */ 63 PLATFORM_CLUSTER_COUNT, 64 /* No of CPU cores - cluster0 */ 65 PLATFORM_MAX_CPUS_PER_CLUSTER, 66 /* No of CPU cores - cluster1 */ 67 PLATFORM_MAX_CPUS_PER_CLUSTER 68 }; 69 70 /******************************************************************************* 71 * This function returns the Tegra default topology tree information. 72 ******************************************************************************/ 73 const unsigned char *plat_get_power_domain_tree_desc(void) 74 { 75 return tegra_power_domain_tree_desc; 76 } 77 78 /******************************************************************************* 79 * Handler to get the System Counter Frequency 80 ******************************************************************************/ 81 unsigned int plat_get_syscnt_freq2(void) 82 { 83 return 19200000; 84 } 85 86 /******************************************************************************* 87 * Maximum supported UART controllers 88 ******************************************************************************/ 89 #define TEGRA210_MAX_UART_PORTS 5 90 91 /******************************************************************************* 92 * This variable holds the UART port base addresses 93 ******************************************************************************/ 94 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 95 0, /* undefined - treated as an error case */ 96 TEGRA_UARTA_BASE, 97 TEGRA_UARTB_BASE, 98 TEGRA_UARTC_BASE, 99 TEGRA_UARTD_BASE, 100 TEGRA_UARTE_BASE, 101 }; 102 103 /******************************************************************************* 104 * Retrieve the UART controller base to be used as the console 105 ******************************************************************************/ 106 uint32_t plat_get_console_from_id(int id) 107 { 108 if (id > TEGRA210_MAX_UART_PORTS) 109 return 0; 110 111 return tegra210_uart_addresses[id]; 112 } 113 114 /******************************************************************************* 115 * Handler for early platform setup 116 ******************************************************************************/ 117 void plat_early_platform_setup(void) 118 { 119 /* Initialize security engine driver */ 120 if (tegra_chipid_is_t210_b01()) { 121 tegra_se_init(); 122 } 123 } 124 125 /******************************************************************************* 126 * Initialize the GIC and SGIs 127 ******************************************************************************/ 128 void plat_gic_setup(void) 129 { 130 tegra_gic_setup(NULL, 0); 131 } 132