1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <lib/mmio.h> 16 17 #include <memctrl.h> 18 #include <tegra_platform.h> 19 #include <tegra_private.h> 20 21 /******************************************************************************* 22 * Common Tegra SiP SMCs 23 ******************************************************************************/ 24 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 25 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 26 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 27 #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 28 29 /******************************************************************************* 30 * Fake system suspend mode control var 31 ******************************************************************************/ 32 extern uint8_t tegra_fake_system_suspend; 33 34 35 /******************************************************************************* 36 * SoC specific SiP handler 37 ******************************************************************************/ 38 #pragma weak plat_sip_handler 39 int plat_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 const void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 /* unused parameters */ 49 (void)smc_fid; 50 (void)x1; 51 (void)x2; 52 (void)x3; 53 (void)x4; 54 (void)cookie; 55 (void)handle; 56 (void)flags; 57 58 return -ENOTSUP; 59 } 60 61 /******************************************************************************* 62 * This function is responsible for handling all SiP calls 63 ******************************************************************************/ 64 uintptr_t tegra_sip_handler(uint32_t smc_fid, 65 u_register_t x1, 66 u_register_t x2, 67 u_register_t x3, 68 u_register_t x4, 69 void *cookie, 70 void *handle, 71 u_register_t flags) 72 { 73 uint32_t regval; 74 int32_t err; 75 76 /* Check if this is a SoC specific SiP */ 77 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 78 if (err == 0) 79 SMC_RET1(handle, (uint64_t)err); 80 81 switch (smc_fid) { 82 83 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 84 85 /* clean up the high bits */ 86 x2 = (uint32_t)x2; 87 88 /* 89 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 90 * or falls outside of the valid DRAM range 91 */ 92 err = bl31_check_ns_address(x1, x2); 93 if (err) 94 SMC_RET1(handle, err); 95 96 /* 97 * Check if Video Memory is aligned to 1MB. 98 */ 99 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 100 ERROR("Unaligned Video Memory base address!\n"); 101 SMC_RET1(handle, -ENOTSUP); 102 } 103 104 /* 105 * The GPU is the user of the Video Memory region. In order to 106 * transition to the new memory region smoothly, we program the 107 * new base/size ONLY if the GPU is in reset mode. 108 */ 109 regval = mmio_read_32(TEGRA_CAR_RESET_BASE + 110 TEGRA_GPU_RESET_REG_OFFSET); 111 if ((regval & GPU_RESET_BIT) == 0U) { 112 ERROR("GPU not in reset! Video Memory setup failed\n"); 113 SMC_RET1(handle, -ENOTSUP); 114 } 115 116 /* new video memory carveout settings */ 117 tegra_memctrl_videomem_setup(x1, x2); 118 119 SMC_RET1(handle, 0); 120 break; 121 122 /* 123 * The NS world registers the address of its handler to be 124 * used for processing the FIQ. This is normally used by the 125 * NS FIQ debugger driver to detect system hangs by programming 126 * a watchdog timer to fire a FIQ interrupt. 127 */ 128 case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 129 130 if (!x1) 131 SMC_RET1(handle, SMC_UNK); 132 133 /* 134 * TODO: Check if x1 contains a valid DRAM address 135 */ 136 137 /* store the NS world's entrypoint */ 138 tegra_fiq_set_ns_entrypoint(x1); 139 140 SMC_RET1(handle, 0); 141 break; 142 143 /* 144 * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 145 * CPU context when the FIQ interrupt was triggered. This allows the 146 * NS world to understand the CPU state when the watchdog interrupt 147 * triggered. 148 */ 149 case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 150 151 /* retrieve context registers when FIQ triggered */ 152 tegra_fiq_get_intr_context(); 153 154 SMC_RET0(handle); 155 break; 156 157 case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 158 /* 159 * System suspend fake mode is set if we are on VDK and we make 160 * a debug SIP call. This mode ensures that we excercise debug 161 * path instead of the regular code path to suit the pre-silicon 162 * platform needs. These include replacing the call to WFI by 163 * a warm reset request. 164 */ 165 if (tegra_platform_is_emulation() != 0U) { 166 167 tegra_fake_system_suspend = 1; 168 SMC_RET1(handle, 0); 169 } 170 171 /* 172 * We return to the external world as if this SIP is not 173 * implemented in case, we are not running on VDK. 174 */ 175 break; 176 177 default: 178 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 179 break; 180 } 181 182 SMC_RET1(handle, SMC_UNK); 183 } 184 185 /* Define a runtime service descriptor for fast SMC calls */ 186 DECLARE_RT_SVC( 187 tegra_sip_fast, 188 189 (OEN_SIP_START), 190 (OEN_SIP_END), 191 (SMC_TYPE_FAST), 192 (NULL), 193 (tegra_sip_handler) 194 ); 195