| 64726e6d | 01-Aug-2017 |
Julius Werner <jwerner@chromium.org> |
Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
H
Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc 00010000 [...] 2**16
10 .text.platform_cpu_warmboot 00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
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|
| 3436089d | 27-Apr-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: delay_timer: fix MISRA defects
Main fixes:
* Include header file for function declarations [Rule 8.4]
* Move global object into function [Rule 8.9]
Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd9
Tegra: delay_timer: fix MISRA defects
Main fixes:
* Include header file for function declarations [Rule 8.4]
* Move global object into function [Rule 8.9]
Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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|
| 9a8f05e4 | 26-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: gic: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible wit
Tegra: gic: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Fixed assert/if statements conditions to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Convert macros form headers to unsigned ints
Change-Id: I8051cc16499cece2039c9751bd347645f40f0901
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 5bd1a177 | 24-Feb-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: fiq_glue: fix MISRA defects
Main fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Convert objec
Tegra: fiq_glue: fix MISRA defects
Main fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Convert object type to match the type of function parameters
[Rule 10.3]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses[Rule 20.7]
Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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|
| 31d97dc2 | 13-Mar-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: pmc: fix defects flagged during MISRA analysis
Main fixes:
* Fixed if/while statement conditional to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if/for/while stateme
Tegra: pmc: fix defects flagged during MISRA analysis
Main fixes:
* Fixed if/while statement conditional to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if/for/while statements in order to
make them compound [Rule 15.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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|
| f5f64e4d | 26-Apr-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl: check GPU reset state from common place
This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.
Change-Id: I3818c5
Tegra: memctrl: check GPU reset state from common place
This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.
Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 14a1c0ed | 25-Jan-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: fix the NS DRAM address calculation logic
This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requireme
Tegra: fix the NS DRAM address calculation logic
This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.
Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 9d42d23a | 21-Dec-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: zero out NS Video memory carveout region
The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
B
Tegra: memctrl_v2: zero out NS Video memory carveout region
The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.
This patch adds the logic to zero out the previous memory carveout
region.
Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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