1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ 8 #define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ 9 10 #define SIZE_K(n) ((n) * 1024) 11 #define SIZE_M(n) ((n) * 1024 * 1024) 12 #define SRAM_TEXT_LIMIT (4 * 1024) 13 #define SRAM_DATA_LIMIT (4 * 1024) 14 #define SRAM_BIN_LIMIT (4 * 1024) 15 16 /* 17 * The parts of the shared defined registers address with AP and M0, 18 * let's note and mark the previous defines like this: 19 */ 20 #define GIC500_BASE (MMIO_BASE + 0x06E00000) 21 #define UART0_BASE (MMIO_BASE + 0x07180000) 22 #define UART1_BASE (MMIO_BASE + 0x07190000) 23 #define UART2_BASE (MMIO_BASE + 0x071A0000) 24 #define UART3_BASE (MMIO_BASE + 0x071B0000) 25 26 #define PMU_BASE (MMIO_BASE + 0x07310000) 27 #define PMUGRF_BASE (MMIO_BASE + 0x07320000) 28 #define SGRF_BASE (MMIO_BASE + 0x07330000) 29 #define PMUSRAM_BASE (MMIO_BASE + 0x073B0000) 30 #define PWM_BASE (MMIO_BASE + 0x07420000) 31 32 #define CIC_BASE (MMIO_BASE + 0x07620000) 33 #define PD_BUS0_BASE (MMIO_BASE + 0x07650000) 34 #define DCF_BASE (MMIO_BASE + 0x076A0000) 35 #define GPIO0_BASE (MMIO_BASE + 0x07720000) 36 #define GPIO1_BASE (MMIO_BASE + 0x07730000) 37 #define PMUCRU_BASE (MMIO_BASE + 0x07750000) 38 #define CRU_BASE (MMIO_BASE + 0x07760000) 39 #define GRF_BASE (MMIO_BASE + 0x07770000) 40 #define GPIO2_BASE (MMIO_BASE + 0x07780000) 41 #define GPIO3_BASE (MMIO_BASE + 0x07788000) 42 #define GPIO4_BASE (MMIO_BASE + 0x07790000) 43 #define STIME_BASE (MMIO_BASE + 0x07860000) 44 #define SRAM_BASE (MMIO_BASE + 0x078C0000) 45 #define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000) 46 #define DDRC0_BASE (MMIO_BASE + 0x07A80000) 47 #define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000) 48 #define DDRC1_BASE (MMIO_BASE + 0x07A88000) 49 #define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000) 50 #define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000) 51 #define CCI500_BASE (MMIO_BASE + 0x07B00000) 52 #define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000) 53 54 /* Registers size */ 55 #define GIC500_SIZE SIZE_M(2) 56 #define UART0_SIZE SIZE_K(64) 57 #define UART1_SIZE SIZE_K(64) 58 #define UART2_SIZE SIZE_K(64) 59 #define UART3_SIZE SIZE_K(64) 60 #define PMU_SIZE SIZE_K(64) 61 #define PMUGRF_SIZE SIZE_K(64) 62 #define SGRF_SIZE SIZE_K(64) 63 #define PMUSRAM_SIZE SIZE_K(64) 64 #define PMUSRAM_RSIZE SIZE_K(8) 65 #define PWM_SIZE SIZE_K(64) 66 #define CIC_SIZE SIZE_K(4) 67 #define DCF_SIZE SIZE_K(4) 68 #define GPIO0_SIZE SIZE_K(64) 69 #define GPIO1_SIZE SIZE_K(64) 70 #define PMUCRU_SIZE SIZE_K(64) 71 #define CRU_SIZE SIZE_K(64) 72 #define GRF_SIZE SIZE_K(64) 73 #define GPIO2_SIZE SIZE_K(32) 74 #define GPIO3_SIZE SIZE_K(32) 75 #define GPIO4_SIZE SIZE_K(32) 76 #define STIME_SIZE SIZE_K(64) 77 #define SRAM_SIZE SIZE_K(192) 78 #define SERVICE_NOC_0_SIZE SIZE_K(192) 79 #define DDRC0_SIZE SIZE_K(32) 80 #define SERVICE_NOC_1_SIZE SIZE_K(16) 81 #define DDRC1_SIZE SIZE_K(32) 82 #define SERVICE_NOC_2_SIZE SIZE_K(16) 83 #define SERVICE_NOC_3_SIZE SIZE_K(448) 84 #define CCI500_SIZE SIZE_M(1) 85 #define PD_BUS0_SIZE SIZE_K(448) 86 87 /* DDR Registers address */ 88 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) 89 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) 90 91 #define PI_OFFSET 0x800 92 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) 93 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) 94 95 #define PHY_OFFSET 0x2000 96 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) 97 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) 98 99 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) 100 101 #endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */ 102