1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <debug.h> 12 13 /* --------------------------------------------- 14 * Disable all types of L2 prefetches. 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_l2_prefetch 18 ldcopr16 r0, r1, CORTEX_A72_ECTLR 19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ 21 CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) 22 stcopr16 r0, r1, CORTEX_A72_ECTLR 23 isb 24 bx lr 25endfunc cortex_a72_disable_l2_prefetch 26 27 /* --------------------------------------------- 28 * Disable the load-store hardware prefetcher. 29 * --------------------------------------------- 30 */ 31func cortex_a72_disable_hw_prefetcher 32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 35 isb 36 dsb ish 37 bx lr 38endfunc cortex_a72_disable_hw_prefetcher 39 40 /* --------------------------------------------- 41 * Disable intra-cluster coherency 42 * Clobbers: r0-r1 43 * --------------------------------------------- 44 */ 45func cortex_a72_disable_smp 46 ldcopr16 r0, r1, CORTEX_A72_ECTLR 47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 48 stcopr16 r0, r1, CORTEX_A72_ECTLR 49 bx lr 50endfunc cortex_a72_disable_smp 51 52 /* --------------------------------------------- 53 * Disable debug interfaces 54 * --------------------------------------------- 55 */ 56func cortex_a72_disable_ext_debug 57 mov r0, #1 58 stcopr r0, DBGOSDLR 59 isb 60 dsb sy 61 bx lr 62endfunc cortex_a72_disable_ext_debug 63 64 /* --------------------------------------------------- 65 * Errata Workaround for Cortex A72 Errata #859971. 66 * This applies only to revision <= r0p3 of Cortex A72. 67 * Inputs: 68 * r0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: r0-r3 70 * --------------------------------------------------- 71 */ 72func errata_a72_859971_wa 73 mov r2,lr 74 bl check_errata_859971 75 mov lr, r2 76 cmp r0, #ERRATA_NOT_APPLIES 77 beq 1f 78 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 79 orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH 80 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 811: 82 bx lr 83endfunc errata_a72_859971_wa 84 85func check_errata_859971 86 mov r1, #0x03 87 b cpu_rev_var_ls 88endfunc check_errata_859971 89 90 91 /* ------------------------------------------------- 92 * The CPU Ops reset function for Cortex-A72. 93 * ------------------------------------------------- 94 */ 95func cortex_a72_reset_func 96 mov r5, lr 97 bl cpu_get_rev_var 98 mov r4, r0 99 100#if ERRATA_A72_859971 101 mov r0, r4 102 bl errata_a72_859971_wa 103#endif 104 /* --------------------------------------------- 105 * Enable the SMP bit. 106 * --------------------------------------------- 107 */ 108 ldcopr16 r0, r1, CORTEX_A72_ECTLR 109 orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 110 stcopr16 r0, r1, CORTEX_A72_ECTLR 111 isb 112 bx lr 113endfunc cortex_a72_reset_func 114 115 /* ---------------------------------------------------- 116 * The CPU Ops core power down function for Cortex-A72. 117 * ---------------------------------------------------- 118 */ 119func cortex_a72_core_pwr_dwn 120 push {r12, lr} 121 122 /* Assert if cache is enabled */ 123#if ASM_ASSERTION 124 ldcopr r0, SCTLR 125 tst r0, #SCTLR_C_BIT 126 ASM_ASSERT(eq) 127#endif 128 129 /* --------------------------------------------- 130 * Disable the L2 prefetches. 131 * --------------------------------------------- 132 */ 133 bl cortex_a72_disable_l2_prefetch 134 135 /* --------------------------------------------- 136 * Disable the load-store hardware prefetcher. 137 * --------------------------------------------- 138 */ 139 bl cortex_a72_disable_hw_prefetcher 140 141 /* --------------------------------------------- 142 * Flush L1 caches. 143 * --------------------------------------------- 144 */ 145 mov r0, #DC_OP_CISW 146 bl dcsw_op_level1 147 148 /* --------------------------------------------- 149 * Come out of intra cluster coherency 150 * --------------------------------------------- 151 */ 152 bl cortex_a72_disable_smp 153 154 /* --------------------------------------------- 155 * Force the debug interfaces to be quiescent 156 * --------------------------------------------- 157 */ 158 pop {r12, lr} 159 b cortex_a72_disable_ext_debug 160endfunc cortex_a72_core_pwr_dwn 161 162 /* ------------------------------------------------------- 163 * The CPU Ops cluster power down function for Cortex-A72. 164 * ------------------------------------------------------- 165 */ 166func cortex_a72_cluster_pwr_dwn 167 push {r12, lr} 168 169 /* Assert if cache is enabled */ 170#if ASM_ASSERTION 171 ldcopr r0, SCTLR 172 tst r0, #SCTLR_C_BIT 173 ASM_ASSERT(eq) 174#endif 175 176 /* --------------------------------------------- 177 * Disable the L2 prefetches. 178 * --------------------------------------------- 179 */ 180 bl cortex_a72_disable_l2_prefetch 181 182 /* --------------------------------------------- 183 * Disable the load-store hardware prefetcher. 184 * --------------------------------------------- 185 */ 186 bl cortex_a72_disable_hw_prefetcher 187 188#if !SKIP_A72_L1_FLUSH_PWR_DWN 189 /* --------------------------------------------- 190 * Flush L1 caches. 191 * --------------------------------------------- 192 */ 193 mov r0, #DC_OP_CISW 194 bl dcsw_op_level1 195#endif 196 197 /* --------------------------------------------- 198 * Disable the optional ACP. 199 * --------------------------------------------- 200 */ 201 bl plat_disable_acp 202 203 /* ------------------------------------------------- 204 * Flush the L2 caches. 205 * ------------------------------------------------- 206 */ 207 mov r0, #DC_OP_CISW 208 bl dcsw_op_level2 209 210 /* --------------------------------------------- 211 * Come out of intra cluster coherency 212 * --------------------------------------------- 213 */ 214 bl cortex_a72_disable_smp 215 216 /* --------------------------------------------- 217 * Force the debug interfaces to be quiescent 218 * --------------------------------------------- 219 */ 220 pop {r12, lr} 221 b cortex_a72_disable_ext_debug 222endfunc cortex_a72_cluster_pwr_dwn 223 224#if REPORT_ERRATA 225/* 226 * Errata printing function for Cortex A72. Must follow AAPCS. 227 */ 228func cortex_a72_errata_report 229 push {r12, lr} 230 231 bl cpu_get_rev_var 232 mov r4, r0 233 234 /* 235 * Report all errata. The revision-variant information is passed to 236 * checking functions of each errata. 237 */ 238 report_errata ERRATA_A72_859971, cortex_a72, 859971 239 240 pop {r12, lr} 241 bx lr 242endfunc cortex_a72_errata_report 243#endif 244 245declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 246 cortex_a72_reset_func, \ 247 cortex_a72_core_pwr_dwn, \ 248 cortex_a72_cluster_pwr_dwn 249