1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <gicv3.h> 9 #include <platform.h> 10 #include <platform_def.h> 11 12 #include "uniphier.h" 13 14 static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 15 16 static const unsigned int g0_interrupt_array[] = { 17 8, /* SGI0 */ 18 14, /* SGI6 */ 19 }; 20 21 static const unsigned int g1s_interrupt_array[] = { 22 29, /* Timer */ 23 9, /* SGI1 */ 24 10, /* SGI2 */ 25 11, /* SGI3 */ 26 12, /* SGI4 */ 27 13, /* SGI5 */ 28 15, /* SGI7 */ 29 }; 30 31 static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr) 32 { 33 return plat_core_pos_by_mpidr(mpidr); 34 } 35 36 static const struct gicv3_driver_data uniphier_gic_driver_data[] = { 37 [UNIPHIER_SOC_LD11] = { 38 .gicd_base = 0x5fe00000, 39 .gicr_base = 0x5fe40000, 40 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 41 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), 42 .g0_interrupt_array = g0_interrupt_array, 43 .g1s_interrupt_array = g1s_interrupt_array, 44 .rdistif_num = PLATFORM_CORE_COUNT, 45 .rdistif_base_addrs = uniphier_rdistif_base_addrs, 46 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, 47 }, 48 [UNIPHIER_SOC_LD20] = { 49 .gicd_base = 0x5fe00000, 50 .gicr_base = 0x5fe80000, 51 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 52 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), 53 .g0_interrupt_array = g0_interrupt_array, 54 .g1s_interrupt_array = g1s_interrupt_array, 55 .rdistif_num = PLATFORM_CORE_COUNT, 56 .rdistif_base_addrs = uniphier_rdistif_base_addrs, 57 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, 58 }, 59 [UNIPHIER_SOC_PXS3] = { 60 .gicd_base = 0x5fe00000, 61 .gicr_base = 0x5fe80000, 62 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 63 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), 64 .g0_interrupt_array = g0_interrupt_array, 65 .g1s_interrupt_array = g1s_interrupt_array, 66 .rdistif_num = PLATFORM_CORE_COUNT, 67 .rdistif_base_addrs = uniphier_rdistif_base_addrs, 68 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos, 69 }, 70 }; 71 72 void uniphier_gic_driver_init(unsigned int soc) 73 { 74 assert(soc < ARRAY_SIZE(uniphier_gic_driver_data)); 75 76 gicv3_driver_init(&uniphier_gic_driver_data[soc]); 77 } 78 79 void uniphier_gic_init(void) 80 { 81 gicv3_distif_init(); 82 gicv3_rdistif_init(plat_my_core_pos()); 83 gicv3_cpuif_enable(plat_my_core_pos()); 84 } 85 86 void uniphier_gic_cpuif_enable(void) 87 { 88 gicv3_cpuif_enable(plat_my_core_pos()); 89 } 90 91 void uniphier_gic_cpuif_disable(void) 92 { 93 gicv3_cpuif_disable(plat_my_core_pos()); 94 } 95 96 void uniphier_gic_pcpu_init(void) 97 { 98 gicv3_rdistif_init(plat_my_core_pos()); 99 } 100