1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <mmio.h> 10 #include <m0_ctl.h> 11 #include <plat_private.h> 12 #include "dfs.h" 13 #include "dram.h" 14 #include "dram_spec_timing.h" 15 #include "string.h" 16 #include "soc.h" 17 #include "pmu.h" 18 19 #include <delay_timer.h> 20 21 #define ENPER_CS_TRAINING_FREQ (666) 22 #define TDFI_LAT_THRESHOLD_FREQ (928) 23 #define PHY_DLL_BYPASS_FREQ (260) 24 25 static const struct pll_div dpll_rates_table[] = { 26 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 37 }; 38 39 struct rk3399_dram_status { 40 uint32_t current_index; 41 uint32_t index_freq[2]; 42 uint32_t boot_freq; 43 uint32_t low_power_stat; 44 struct timing_related_config timing_config; 45 struct drv_odt_lp_config drv_odt_lp_cfg; 46 }; 47 48 struct rk3399_saved_status { 49 uint32_t freq; 50 uint32_t low_power_stat; 51 uint32_t odt; 52 }; 53 54 static struct rk3399_dram_status rk3399_dram_status; 55 static struct rk3399_saved_status rk3399_suspend_status; 56 static uint32_t wrdqs_delay_val[2][2][4]; 57 static uint32_t rddqs_delay_ps; 58 59 static struct rk3399_sdram_default_config ddr3_default_config = { 60 .bl = 8, 61 .ap = 0, 62 .burst_ref_cnt = 1, 63 .zqcsi = 0 64 }; 65 66 static struct rk3399_sdram_default_config lpddr3_default_config = { 67 .bl = 8, 68 .ap = 0, 69 .burst_ref_cnt = 1, 70 .zqcsi = 0 71 }; 72 73 static struct rk3399_sdram_default_config lpddr4_default_config = { 74 .bl = 16, 75 .ap = 0, 76 .caodt = 240, 77 .burst_ref_cnt = 1, 78 .zqcsi = 0 79 }; 80 81 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 82 uint8_t channel, uint8_t cs) 83 { 84 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 85 uint32_t bandwidth; 86 uint32_t die_bandwidth; 87 uint32_t die; 88 uint32_t cs_cap; 89 uint32_t row; 90 91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 92 bandwidth = 8 * (1 << ch->bw); 93 die_bandwidth = 8 * (1 << ch->dbw); 94 die = bandwidth / die_bandwidth; 95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 96 (bandwidth / 16))); 97 if (ch->row_3_4) 98 cs_cap = cs_cap * 3 / 4; 99 100 return (cs_cap / die); 101 } 102 103 static void get_dram_drv_odt_val(uint32_t dram_type, 104 struct drv_odt_lp_config *drv_config) 105 { 106 uint32_t tmp; 107 uint32_t mr1_val, mr3_val, mr11_val; 108 109 switch (dram_type) { 110 case DDR3: 111 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 112 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 113 if (tmp) 114 drv_config->dram_side_drv = 34; 115 else 116 drv_config->dram_side_drv = 40; 117 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 118 ((mr1_val >> 7) & 1); 119 if (tmp == 0) 120 drv_config->dram_side_dq_odt = 0; 121 else if (tmp == 1) 122 drv_config->dram_side_dq_odt = 60; 123 else if (tmp == 3) 124 drv_config->dram_side_dq_odt = 40; 125 else 126 drv_config->dram_side_dq_odt = 120; 127 break; 128 case LPDDR3: 129 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 130 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 131 if (mr3_val == 0xb) 132 drv_config->dram_side_drv = 3448; 133 else if (mr3_val == 0xa) 134 drv_config->dram_side_drv = 4048; 135 else if (mr3_val == 0x9) 136 drv_config->dram_side_drv = 3440; 137 else if (mr3_val == 0x4) 138 drv_config->dram_side_drv = 60; 139 else if (mr3_val == 0x3) 140 drv_config->dram_side_drv = 48; 141 else if (mr3_val == 0x2) 142 drv_config->dram_side_drv = 40; 143 else 144 drv_config->dram_side_drv = 34; 145 146 if (mr11_val == 1) 147 drv_config->dram_side_dq_odt = 60; 148 else if (mr11_val == 2) 149 drv_config->dram_side_dq_odt = 120; 150 else if (mr11_val == 0) 151 drv_config->dram_side_dq_odt = 0; 152 else 153 drv_config->dram_side_dq_odt = 240; 154 break; 155 case LPDDR4: 156 default: 157 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 158 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 159 160 if ((mr3_val == 0) || (mr3_val == 7)) 161 drv_config->dram_side_drv = 40; 162 else 163 drv_config->dram_side_drv = 240 / mr3_val; 164 165 tmp = mr11_val & 0x7; 166 if ((tmp == 7) || (tmp == 0)) 167 drv_config->dram_side_dq_odt = 0; 168 else 169 drv_config->dram_side_dq_odt = 240 / tmp; 170 171 tmp = (mr11_val >> 4) & 0x7; 172 if ((tmp == 7) || (tmp == 0)) 173 drv_config->dram_side_ca_odt = 0; 174 else 175 drv_config->dram_side_ca_odt = 240 / tmp; 176 break; 177 } 178 } 179 180 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 181 struct rk3399_sdram_params *sdram_params, 182 struct drv_odt_lp_config *drv_config) 183 { 184 uint32_t i, j; 185 186 for (i = 0; i < sdram_params->num_channels; i++) { 187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 189 for (j = 0; j < sdram_params->ch[i].rank; j++) { 190 ptiming_config->dram_info[i].per_die_capability[j] = 191 get_cs_die_capability(sdram_params, i, j); 192 } 193 } 194 ptiming_config->dram_type = sdram_params->dramtype; 195 ptiming_config->ch_cnt = sdram_params->num_channels; 196 switch (sdram_params->dramtype) { 197 case DDR3: 198 ptiming_config->bl = ddr3_default_config.bl; 199 ptiming_config->ap = ddr3_default_config.ap; 200 break; 201 case LPDDR3: 202 ptiming_config->bl = lpddr3_default_config.bl; 203 ptiming_config->ap = lpddr3_default_config.ap; 204 break; 205 case LPDDR4: 206 ptiming_config->bl = lpddr4_default_config.bl; 207 ptiming_config->ap = lpddr4_default_config.ap; 208 ptiming_config->rdbi = 0; 209 ptiming_config->wdbi = 0; 210 break; 211 } 212 ptiming_config->dramds = drv_config->dram_side_drv; 213 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 214 ptiming_config->caodt = drv_config->dram_side_ca_odt; 215 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 216 } 217 218 struct lat_adj_pair { 219 uint32_t cl; 220 uint32_t rdlat_adj; 221 uint32_t cwl; 222 uint32_t wrlat_adj; 223 }; 224 225 const struct lat_adj_pair ddr3_lat_adj[] = { 226 {6, 5, 5, 4}, 227 {8, 7, 6, 5}, 228 {10, 9, 7, 6}, 229 {11, 9, 8, 7}, 230 {13, 0xb, 9, 8}, 231 {14, 0xb, 0xa, 9} 232 }; 233 234 const struct lat_adj_pair lpddr3_lat_adj[] = { 235 {3, 2, 1, 0}, 236 {6, 5, 3, 2}, 237 {8, 7, 4, 3}, 238 {9, 8, 5, 4}, 239 {10, 9, 6, 5}, 240 {11, 9, 6, 5}, 241 {12, 0xa, 6, 5}, 242 {14, 0xc, 8, 7}, 243 {16, 0xd, 8, 7} 244 }; 245 246 const struct lat_adj_pair lpddr4_lat_adj[] = { 247 {6, 5, 4, 2}, 248 {10, 9, 6, 4}, 249 {14, 0xc, 8, 6}, 250 {20, 0x11, 0xa, 8}, 251 {24, 0x15, 0xc, 0xa}, 252 {28, 0x18, 0xe, 0xc}, 253 {32, 0x1b, 0x10, 0xe}, 254 {36, 0x1e, 0x12, 0x10} 255 }; 256 257 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 258 { 259 const struct lat_adj_pair *p; 260 uint32_t cnt; 261 uint32_t i; 262 263 if (dram_type == DDR3) { 264 p = ddr3_lat_adj; 265 cnt = ARRAY_SIZE(ddr3_lat_adj); 266 } else if (dram_type == LPDDR3) { 267 p = lpddr3_lat_adj; 268 cnt = ARRAY_SIZE(lpddr3_lat_adj); 269 } else { 270 p = lpddr4_lat_adj; 271 cnt = ARRAY_SIZE(lpddr4_lat_adj); 272 } 273 274 for (i = 0; i < cnt; i++) { 275 if (cl == p[i].cl) 276 return p[i].rdlat_adj; 277 } 278 /* fail */ 279 return 0xff; 280 } 281 282 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 283 { 284 const struct lat_adj_pair *p; 285 uint32_t cnt; 286 uint32_t i; 287 288 if (dram_type == DDR3) { 289 p = ddr3_lat_adj; 290 cnt = ARRAY_SIZE(ddr3_lat_adj); 291 } else if (dram_type == LPDDR3) { 292 p = lpddr3_lat_adj; 293 cnt = ARRAY_SIZE(lpddr3_lat_adj); 294 } else { 295 p = lpddr4_lat_adj; 296 cnt = ARRAY_SIZE(lpddr4_lat_adj); 297 } 298 299 for (i = 0; i < cnt; i++) { 300 if (cwl == p[i].cwl) 301 return p[i].wrlat_adj; 302 } 303 /* fail */ 304 return 0xff; 305 } 306 307 #define PI_REGS_DIMM_SUPPORT (0) 308 #define PI_ADD_LATENCY (0) 309 #define PI_DOUBLEFREEK (1) 310 311 #define PI_PAD_DELAY_PS_VALUE (1000) 312 #define PI_IE_ENABLE_VALUE (3000) 313 #define PI_TSEL_ENABLE_VALUE (700) 314 315 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 316 { 317 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 318 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 319 extra_adder, tsel_enable; 320 321 ie_enable = PI_IE_ENABLE_VALUE; 322 tsel_enable = PI_TSEL_ENABLE_VALUE; 323 324 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 325 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 326 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 327 delay_adder++; 328 hs_offset = 0; 329 tsel_adder = 0; 330 extra_adder = 0; 331 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 332 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 333 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 334 tsel_adder++; 335 delay_adder = delay_adder - 1; 336 if (tsel_adder > delay_adder) 337 extra_adder = tsel_adder - delay_adder; 338 else 339 extra_adder = 0; 340 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 341 hs_offset = 2; 342 else 343 hs_offset = 1; 344 345 if (delay_adder > (rdlat - 1 - hs_offset)) { 346 rdlat = rdlat - tsel_adder; 347 } else { 348 if ((rdlat - delay_adder) < 2) 349 rdlat = 2; 350 else 351 rdlat = rdlat - delay_adder - extra_adder; 352 } 353 354 return rdlat; 355 } 356 357 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 358 struct timing_related_config *timing_config) 359 { 360 uint32_t tmp; 361 362 if (timing_config->dram_type == LPDDR3) { 363 tmp = pdram_timing->cl; 364 if (tmp >= 14) 365 tmp = 8; 366 else if (tmp >= 10) 367 tmp = 6; 368 else if (tmp == 9) 369 tmp = 5; 370 else if (tmp == 8) 371 tmp = 4; 372 else if (tmp == 6) 373 tmp = 3; 374 else 375 tmp = 1; 376 } else { 377 tmp = 1; 378 } 379 380 return tmp; 381 } 382 383 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 384 struct timing_related_config *timing_config) 385 { 386 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 387 } 388 389 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 390 struct timing_related_config *timing_config) 391 { 392 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 393 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 394 uint32_t mem_delay_ps, round_trip_ps; 395 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 396 397 ie_enable = PI_IE_ENABLE_VALUE; 398 399 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 400 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 401 delay_adder++; 402 delay_adder = delay_adder - 1; 403 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 404 hs_offset = 2; 405 else 406 hs_offset = 1; 407 408 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 409 410 if (delay_adder > (cas_lat - 1 - hs_offset)) { 411 ie_delay_adder = 0; 412 } else { 413 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 414 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 415 ie_delay_adder++; 416 } 417 418 if (timing_config->dram_type == DDR3) { 419 mem_delay_ps = 0; 420 } else if (timing_config->dram_type == LPDDR4) { 421 mem_delay_ps = 3600; 422 } else if (timing_config->dram_type == LPDDR3) { 423 mem_delay_ps = 5500; 424 } else { 425 NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 426 return 0; 427 } 428 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 429 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 430 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 431 delay_adder++; 432 433 phy_internal_delay = 5 + 2 + 4; 434 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 435 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 436 lpddr_adder++; 437 dfi_adder = 0; 438 phy_internal_delay = phy_internal_delay + 2; 439 rdlat_delay = delay_adder + phy_internal_delay + 440 ie_delay_adder + lpddr_adder + dfi_adder; 441 442 rdlat_delay = rdlat_delay + 2; 443 return rdlat_delay; 444 } 445 446 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 447 struct timing_related_config *timing_config) 448 { 449 uint32_t tmp, todtoff_min_ps; 450 451 if (timing_config->dram_type == LPDDR3) 452 todtoff_min_ps = 2500; 453 else if (timing_config->dram_type == LPDDR4) 454 todtoff_min_ps = 1500; 455 else 456 todtoff_min_ps = 0; 457 /* todtoff_min */ 458 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 459 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 460 tmp++; 461 return tmp; 462 } 463 464 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 465 struct timing_related_config *timing_config) 466 { 467 uint32_t tmp, todtoff_max_ps; 468 469 if ((timing_config->dram_type == LPDDR4) 470 || (timing_config->dram_type == LPDDR3)) 471 todtoff_max_ps = 3500; 472 else 473 todtoff_max_ps = 0; 474 475 /* todtoff_max */ 476 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 477 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 478 tmp++; 479 return tmp; 480 } 481 482 static void gen_rk3399_ctl_params_f0(struct timing_related_config 483 *timing_config, 484 struct dram_timing_t *pdram_timing) 485 { 486 uint32_t i; 487 uint32_t tmp, tmp1; 488 489 for (i = 0; i < timing_config->ch_cnt; i++) { 490 if (timing_config->dram_type == DDR3) { 491 tmp = ((700000 + 10) * timing_config->freq + 492 999) / 1000; 493 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 494 pdram_timing->tmod + pdram_timing->tzqinit; 495 mmio_write_32(CTL_REG(i, 5), tmp); 496 497 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 498 pdram_timing->tdllk); 499 500 mmio_write_32(CTL_REG(i, 32), 501 (pdram_timing->tmod << 8) | 502 pdram_timing->tmrd); 503 504 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 505 (pdram_timing->txsr - 506 pdram_timing->trcd) << 16); 507 } else if (timing_config->dram_type == LPDDR4) { 508 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 509 pdram_timing->tinit3); 510 mmio_write_32(CTL_REG(i, 32), 511 (pdram_timing->tmrd << 8) | 512 pdram_timing->tmrd); 513 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 514 pdram_timing->txsr << 16); 515 } else { 516 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 517 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 518 mmio_write_32(CTL_REG(i, 32), 519 (pdram_timing->tmrd << 8) | 520 pdram_timing->tmrd); 521 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 522 pdram_timing->txsr << 16); 523 } 524 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 525 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 526 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 527 ((pdram_timing->cl * 2) << 16)); 528 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 529 (pdram_timing->cwl << 24)); 530 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 531 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 532 (pdram_timing->trc << 24) | 533 (pdram_timing->trrd << 16)); 534 mmio_write_32(CTL_REG(i, 27), 535 (pdram_timing->tfaw << 24) | 536 (pdram_timing->trppb << 16) | 537 (pdram_timing->twtr << 8) | 538 pdram_timing->tras_min); 539 540 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 541 max(4, pdram_timing->trtp) << 24); 542 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 543 pdram_timing->tras_max); 544 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 545 max(1, pdram_timing->tckesr)); 546 mmio_clrsetbits_32(CTL_REG(i, 39), 547 (0x3f << 16) | (0xff << 8), 548 (pdram_timing->twr << 16) | 549 (pdram_timing->trcd << 8)); 550 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 551 pdram_timing->tmrz << 16); 552 tmp = pdram_timing->tdal ? pdram_timing->tdal : 553 (pdram_timing->twr + pdram_timing->trp); 554 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 555 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 556 mmio_write_32(CTL_REG(i, 48), 557 ((pdram_timing->trefi - 8) << 16) | 558 pdram_timing->trfc); 559 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 560 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 561 pdram_timing->txpdll << 16); 562 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 563 pdram_timing->tcscke << 24); 564 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 565 mmio_write_32(CTL_REG(i, 56), 566 (pdram_timing->tzqcke << 24) | 567 (pdram_timing->tmrwckel << 16) | 568 (pdram_timing->tckehcs << 8) | 569 pdram_timing->tckelcs); 570 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 571 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 572 (pdram_timing->tckehcmd << 24) | 573 (pdram_timing->tckelcmd << 16)); 574 mmio_write_32(CTL_REG(i, 63), 575 (pdram_timing->tckelpd << 24) | 576 (pdram_timing->tescke << 16) | 577 (pdram_timing->tsr << 8) | 578 pdram_timing->tckckel); 579 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 580 (pdram_timing->tcmdcke << 8) | 581 pdram_timing->tcsckeh); 582 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 583 (pdram_timing->tcksrx << 16) | 584 (pdram_timing->tcksre << 8)); 585 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 586 (timing_config->dllbp << 24)); 587 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 588 (pdram_timing->tvrcg_enable << 16)); 589 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 590 pdram_timing->tvrcg_disable); 591 mmio_write_32(CTL_REG(i, 124), 592 (pdram_timing->tvref_long << 16) | 593 (pdram_timing->tckfspx << 8) | 594 pdram_timing->tckfspe); 595 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 596 pdram_timing->mr[0]); 597 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 598 pdram_timing->mr[2]); 599 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 600 pdram_timing->mr[3]); 601 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 602 pdram_timing->mr11 << 24); 603 mmio_write_32(CTL_REG(i, 147), 604 (pdram_timing->mr[1] << 16) | 605 pdram_timing->mr[0]); 606 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 607 pdram_timing->mr[2]); 608 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 609 pdram_timing->mr[3]); 610 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 611 pdram_timing->mr11 << 24); 612 if (timing_config->dram_type == LPDDR4) { 613 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 614 pdram_timing->mr12 << 16); 615 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 616 pdram_timing->mr14 << 16); 617 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 618 pdram_timing->mr22 << 16); 619 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 620 pdram_timing->mr12 << 16); 621 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 622 pdram_timing->mr14 << 16); 623 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 624 pdram_timing->mr22 << 16); 625 } 626 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 627 pdram_timing->tzqinit << 8); 628 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 629 (pdram_timing->tzqinit / 2)); 630 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 631 pdram_timing->tzqcal); 632 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 633 pdram_timing->todton << 8); 634 635 if (timing_config->odt) { 636 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 637 if (timing_config->freq < 400) 638 tmp = 4 << 24; 639 else 640 tmp = 8 << 24; 641 } else { 642 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 643 tmp = 2 << 24; 644 } 645 646 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 647 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 648 (pdram_timing->tdqsck << 16) | 649 (pdram_timing->tdqsck_max << 8)); 650 tmp = 651 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 652 << 8) | get_rdlat_adj(timing_config->dram_type, 653 pdram_timing->cl); 654 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 655 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 656 (4 * pdram_timing->trefi) << 16); 657 658 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 659 (2 * pdram_timing->trefi) & 0xffff); 660 661 if ((timing_config->dram_type == LPDDR3) || 662 (timing_config->dram_type == LPDDR4)) { 663 tmp = get_pi_wrlat(pdram_timing, timing_config); 664 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 665 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 666 } else { 667 tmp = 0; 668 } 669 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 670 (tmp & 0x3f) << 16); 671 672 if ((timing_config->dram_type == LPDDR3) || 673 (timing_config->dram_type == LPDDR4)) { 674 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 675 tmp = pdram_timing->cl + 676 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 677 /* todtoff_max */ 678 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 679 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 680 } else { 681 tmp = pdram_timing->cl - pdram_timing->cwl; 682 } 683 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 684 (tmp & 0x3f) << 8); 685 686 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 687 (get_pi_tdfi_phy_rdlat(pdram_timing, 688 timing_config) & 689 0xff) << 16); 690 691 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 692 (2 * pdram_timing->trefi) & 0xffff); 693 694 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 695 (2 * pdram_timing->trefi) & 0xffff); 696 697 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 698 699 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 700 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 701 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 702 tmp1++; 703 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 704 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 705 706 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 707 tmp = tmp + 18; 708 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 709 710 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 711 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 712 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 713 if (tmp1 == 0) 714 tmp = 0; 715 else if (tmp1 < 5) 716 tmp = tmp1 - 1; 717 else 718 tmp = tmp1 - 5; 719 } else { 720 tmp = tmp1 - 2; 721 } 722 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 723 724 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 725 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 726 (pdram_timing->cl >= 5)) 727 tmp = pdram_timing->cl - 5; 728 else 729 tmp = pdram_timing->cl - 2; 730 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 731 } 732 } 733 734 static void gen_rk3399_ctl_params_f1(struct timing_related_config 735 *timing_config, 736 struct dram_timing_t *pdram_timing) 737 { 738 uint32_t i; 739 uint32_t tmp, tmp1; 740 741 for (i = 0; i < timing_config->ch_cnt; i++) { 742 if (timing_config->dram_type == DDR3) { 743 tmp = 744 ((700000 + 10) * timing_config->freq + 999) / 1000; 745 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 746 pdram_timing->tmod + pdram_timing->tzqinit; 747 mmio_write_32(CTL_REG(i, 9), tmp); 748 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 749 pdram_timing->tdllk << 16); 750 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 751 (pdram_timing->tmod << 24) | 752 (pdram_timing->tmrd << 16) | 753 (pdram_timing->trtp << 8)); 754 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 755 (pdram_timing->txsr - 756 pdram_timing->trcd) << 16); 757 } else if (timing_config->dram_type == LPDDR4) { 758 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 759 pdram_timing->tinit3); 760 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 761 (pdram_timing->tmrd << 24) | 762 (pdram_timing->tmrd << 16) | 763 (pdram_timing->trtp << 8)); 764 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 765 pdram_timing->txsr << 16); 766 } else { 767 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 768 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 769 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 770 (pdram_timing->tmrd << 24) | 771 (pdram_timing->tmrd << 16) | 772 (pdram_timing->trtp << 8)); 773 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 774 pdram_timing->txsr << 16); 775 } 776 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 777 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 778 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 779 ((pdram_timing->cl * 2) << 8)); 780 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 781 (pdram_timing->cwl << 16)); 782 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 783 pdram_timing->al << 24); 784 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 785 (pdram_timing->tras_min << 24) | 786 (pdram_timing->trc << 16) | 787 (pdram_timing->trrd << 8)); 788 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 789 (pdram_timing->tfaw << 16) | 790 (pdram_timing->trppb << 8) | 791 pdram_timing->twtr); 792 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 793 pdram_timing->tras_max); 794 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 795 max(1, pdram_timing->tckesr)); 796 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 797 (pdram_timing->trcd << 24)); 798 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 799 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 800 pdram_timing->tmrz << 24); 801 tmp = pdram_timing->tdal ? pdram_timing->tdal : 802 (pdram_timing->twr + pdram_timing->trp); 803 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 804 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 805 pdram_timing->trp << 8); 806 mmio_write_32(CTL_REG(i, 49), 807 ((pdram_timing->trefi - 8) << 16) | 808 pdram_timing->trfc); 809 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 810 pdram_timing->txp << 16); 811 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 812 pdram_timing->txpdll); 813 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 814 pdram_timing->tmrri << 8); 815 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 816 (pdram_timing->tckehcs << 16) | 817 (pdram_timing->tckelcs << 8) | 818 pdram_timing->tcscke); 819 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 820 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 821 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 822 (pdram_timing->tckehcmd << 24) | 823 (pdram_timing->tckelcmd << 16)); 824 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 825 (pdram_timing->tescke << 16) | 826 (pdram_timing->tsr << 8) | 827 pdram_timing->tckckel); 828 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 829 (pdram_timing->tcmdcke << 8) | 830 pdram_timing->tcsckeh); 831 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 832 (pdram_timing->tcksre << 24)); 833 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 834 pdram_timing->tcksrx); 835 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 836 (timing_config->dllbp << 25)); 837 mmio_write_32(CTL_REG(i, 125), 838 (pdram_timing->tvrcg_disable << 16) | 839 pdram_timing->tvrcg_enable); 840 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 841 (pdram_timing->tckfspe << 16) | 842 pdram_timing->tfc_long); 843 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 844 pdram_timing->tvref_long); 845 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 846 pdram_timing->mr[0] << 16); 847 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 848 pdram_timing->mr[1]); 849 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 850 pdram_timing->mr[3] << 16); 851 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 852 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 853 pdram_timing->mr[0] << 16); 854 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 855 pdram_timing->mr[1]); 856 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 857 pdram_timing->mr[3] << 16); 858 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 859 if (timing_config->dram_type == LPDDR4) { 860 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 861 pdram_timing->mr12); 862 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 863 pdram_timing->mr14); 864 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 865 pdram_timing->mr22); 866 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 867 pdram_timing->mr12); 868 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 869 pdram_timing->mr14); 870 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 871 pdram_timing->mr22); 872 } 873 mmio_write_32(CTL_REG(i, 182), 874 ((pdram_timing->tzqinit / 2) << 16) | 875 pdram_timing->tzqinit); 876 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 877 pdram_timing->tzqcs); 878 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 879 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 880 pdram_timing->tzqreset); 881 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 882 pdram_timing->todton << 16); 883 884 if (timing_config->odt) { 885 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 886 if (timing_config->freq < 400) 887 tmp = 4 << 24; 888 else 889 tmp = 8 << 24; 890 } else { 891 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 892 tmp = 2 << 24; 893 } 894 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 895 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 896 (pdram_timing->tdqsck_max << 24)); 897 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 898 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 899 (get_wrlat_adj(timing_config->dram_type, 900 pdram_timing->cwl) << 8) | 901 get_rdlat_adj(timing_config->dram_type, 902 pdram_timing->cl)); 903 904 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 905 (4 * pdram_timing->trefi) & 0xffff); 906 907 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 908 ((2 * pdram_timing->trefi) & 0xffff) << 16); 909 910 if ((timing_config->dram_type == LPDDR3) || 911 (timing_config->dram_type == LPDDR4)) { 912 tmp = get_pi_wrlat(pdram_timing, timing_config); 913 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 914 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 915 } else { 916 tmp = 0; 917 } 918 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 919 (tmp & 0x3f) << 24); 920 921 if ((timing_config->dram_type == LPDDR3) || 922 (timing_config->dram_type == LPDDR4)) { 923 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 924 tmp = pdram_timing->cl + 925 get_pi_todtoff_min(pdram_timing, timing_config); 926 tmp--; 927 /* todtoff_max */ 928 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 929 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 930 } else { 931 tmp = pdram_timing->cl - pdram_timing->cwl; 932 } 933 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 934 (tmp & 0x3f) << 16); 935 936 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 937 (get_pi_tdfi_phy_rdlat(pdram_timing, 938 timing_config) & 939 0xff) << 24); 940 941 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 942 ((2 * pdram_timing->trefi) & 0xffff) << 16); 943 944 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 945 (2 * pdram_timing->trefi) & 0xffff); 946 947 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 948 949 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 950 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 951 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 952 tmp1++; 953 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 954 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 955 956 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 957 tmp = tmp + 18; 958 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 959 960 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 961 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 962 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 963 if (tmp1 == 0) 964 tmp = 0; 965 else if (tmp1 < 5) 966 tmp = tmp1 - 1; 967 else 968 tmp = tmp1 - 5; 969 } else { 970 tmp = tmp1 - 2; 971 } 972 973 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 974 975 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 976 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 977 (pdram_timing->cl >= 5)) 978 tmp = pdram_timing->cl - 5; 979 else 980 tmp = pdram_timing->cl - 2; 981 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 982 } 983 } 984 985 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 986 { 987 uint32_t i, tmp; 988 989 if (nmhz <= PHY_DLL_BYPASS_FREQ) 990 tmp = 0; 991 else 992 tmp = 1; 993 994 for (i = 0; i < ch_cnt; i++) { 995 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 996 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 997 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); 998 } 999 } 1000 1001 static void gen_rk3399_disable_training(uint32_t ch_cnt) 1002 { 1003 uint32_t i; 1004 1005 for (i = 0; i < ch_cnt; i++) { 1006 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); 1007 mmio_clrbits_32(CTL_REG(i, 71), 1); 1008 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); 1009 } 1010 } 1011 1012 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1013 struct dram_timing_t *pdram_timing, 1014 uint32_t fn) 1015 { 1016 if (fn == 0) 1017 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1018 else 1019 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1020 } 1021 1022 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1023 struct dram_timing_t *pdram_timing) 1024 { 1025 uint32_t tmp, tmp1, tmp2; 1026 uint32_t i; 1027 1028 for (i = 0; i < timing_config->ch_cnt; i++) { 1029 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1030 tmp = 4 * pdram_timing->trefi; 1031 mmio_write_32(PI_REG(i, 2), tmp); 1032 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1033 tmp = 2 * pdram_timing->trefi; 1034 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1035 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1036 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1037 1038 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1039 if (timing_config->dram_type == LPDDR4) 1040 tmp = 2; 1041 else 1042 tmp = 0; 1043 tmp = (pdram_timing->bl / 2) + 4 + 1044 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1045 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1046 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1047 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1048 if (timing_config->dram_type == LPDDR3) { 1049 tmp = get_pi_wrlat(pdram_timing, timing_config); 1050 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1051 } 1052 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1053 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1054 PI_ADD_LATENCY << 8); 1055 1056 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1057 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1058 (pdram_timing->cl * 2) << 16); 1059 /* PI_46 PI_TREF_F0:RW:16:16 */ 1060 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1061 pdram_timing->trefi << 16); 1062 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1063 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1064 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1065 if (timing_config->dram_type == LPDDR3) { 1066 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1067 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1068 tmp << 24); 1069 } 1070 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1071 if ((timing_config->dram_type == LPDDR3) || 1072 (timing_config->dram_type == LPDDR4)) { 1073 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1074 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1075 if (tmp1 > tmp2) 1076 tmp = tmp1 - tmp2; 1077 else 1078 tmp = 0; 1079 } else if (timing_config->dram_type == DDR3) { 1080 tmp = 0; 1081 } 1082 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1083 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1084 if ((timing_config->dram_type == LPDDR3) || 1085 (timing_config->dram_type == LPDDR4)) { 1086 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1087 tmp1 = pdram_timing->cl; 1088 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1089 tmp1--; 1090 /* todtoff_max */ 1091 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1092 if (tmp1 > tmp2) 1093 tmp = tmp1 - tmp2; 1094 else 1095 tmp = 0; 1096 } else if (timing_config->dram_type == DDR3) { 1097 tmp = pdram_timing->cl - pdram_timing->cwl; 1098 } 1099 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1100 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1101 tmp = get_pi_rdlat_adj(pdram_timing); 1102 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1103 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1104 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1105 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1106 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1107 tmp1 = tmp; 1108 if (tmp1 == 0) 1109 tmp = 0; 1110 else if (tmp1 < 5) 1111 tmp = tmp1 - 1; 1112 else 1113 tmp = tmp1 - 5; 1114 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1115 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1116 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1117 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1118 tmp1++; 1119 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1120 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1121 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1122 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1123 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1124 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1125 pdram_timing->tmrz << 8); 1126 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1127 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1128 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1129 tmp1++; 1130 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1131 tmp = tmp1 + 5; 1132 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1133 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1134 tmp = 10000 / (1000000 / pdram_timing->mhz); 1135 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1136 tmp++; 1137 if (pdram_timing->mhz <= 100) 1138 tmp = tmp + 1; 1139 else 1140 tmp = tmp + 8; 1141 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1142 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1143 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1144 pdram_timing->mr[1] << 8); 1145 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1146 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1147 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1148 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1149 pdram_timing->mr[1] << 16); 1150 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1151 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1152 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1153 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1154 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1155 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1156 pdram_timing->mr[2] << 16); 1157 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1158 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1159 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1160 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1161 pdram_timing->mr[2] << 16); 1162 /* PI_156 PI_TFC_F0:RW:0:10 */ 1163 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, 1164 pdram_timing->tfc_long); 1165 /* PI_158 PI_TWR_F0:RW:24:6 */ 1166 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1167 pdram_timing->twr << 24); 1168 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1169 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1170 pdram_timing->twtr << 16); 1171 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1172 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1173 pdram_timing->trcd << 8); 1174 /* PI_158 PI_TRP_F0:RW:0:8 */ 1175 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1176 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1177 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1178 pdram_timing->trtp << 24); 1179 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1180 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1181 pdram_timing->tras_min << 24); 1182 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1183 tmp = pdram_timing->tras_max * 99 / 100; 1184 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1185 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1186 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1187 pdram_timing->tmrd << 16); 1188 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1189 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1190 pdram_timing->tdqsck_max); 1191 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1192 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1193 (2 * pdram_timing->trefi) << 8); 1194 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1195 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1196 20 * pdram_timing->trefi); 1197 } 1198 } 1199 1200 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1201 struct dram_timing_t *pdram_timing) 1202 { 1203 uint32_t tmp, tmp1, tmp2; 1204 uint32_t i; 1205 1206 for (i = 0; i < timing_config->ch_cnt; i++) { 1207 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1208 tmp = 4 * pdram_timing->trefi; 1209 mmio_write_32(PI_REG(i, 4), tmp); 1210 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1211 tmp = 2 * pdram_timing->trefi; 1212 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1213 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1214 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1215 1216 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1217 if (timing_config->dram_type == LPDDR4) 1218 tmp = 2; 1219 else 1220 tmp = 0; 1221 tmp = (pdram_timing->bl / 2) + 4 + 1222 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1223 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1224 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1225 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1226 if (timing_config->dram_type == LPDDR3) { 1227 tmp = get_pi_wrlat(pdram_timing, timing_config); 1228 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1229 tmp << 24); 1230 } 1231 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1232 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1233 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1234 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1235 (pdram_timing->cl * 2) << 8); 1236 /* PI_47 PI_TREF_F1:RW:16:16 */ 1237 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1238 pdram_timing->trefi << 16); 1239 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1240 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1241 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1242 if (timing_config->dram_type == LPDDR3) { 1243 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1244 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1245 } 1246 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1247 if ((timing_config->dram_type == LPDDR3) || 1248 (timing_config->dram_type == LPDDR4)) { 1249 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1250 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1251 if (tmp1 > tmp2) 1252 tmp = tmp1 - tmp2; 1253 else 1254 tmp = 0; 1255 } else if (timing_config->dram_type == DDR3) { 1256 tmp = 0; 1257 } 1258 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1259 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1260 if ((timing_config->dram_type == LPDDR3) || 1261 (timing_config->dram_type == LPDDR4)) { 1262 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1263 tmp1 = pdram_timing->cl + 1264 get_pi_todtoff_min(pdram_timing, timing_config); 1265 tmp1--; 1266 /* todtoff_max */ 1267 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1268 if (tmp1 > tmp2) 1269 tmp = tmp1 - tmp2; 1270 else 1271 tmp = 0; 1272 } else if (timing_config->dram_type == DDR3) 1273 tmp = pdram_timing->cl - pdram_timing->cwl; 1274 1275 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1276 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1277 tmp = get_pi_rdlat_adj(pdram_timing); 1278 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1279 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1280 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1281 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1282 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1283 tmp1 = tmp; 1284 if (tmp1 == 0) 1285 tmp = 0; 1286 else if (tmp1 < 5) 1287 tmp = tmp1 - 1; 1288 else 1289 tmp = tmp1 - 5; 1290 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1291 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1292 /* tadr=20ns */ 1293 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1294 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1295 tmp1++; 1296 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1297 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1298 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1299 tmp = tmp + 18; 1300 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1301 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1302 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1303 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1304 /* tds_train=ceil(2/ns) */ 1305 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1306 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1307 tmp1++; 1308 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1309 tmp = tmp1 + 5; 1310 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1311 tmp << 16); 1312 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1313 tmp = 10000 / (1000000 / pdram_timing->mhz); 1314 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1315 tmp++; 1316 if (pdram_timing->mhz <= 100) 1317 tmp = tmp + 1; 1318 else 1319 tmp = tmp + 8; 1320 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1321 tmp << 24); 1322 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1323 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1324 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1325 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1326 pdram_timing->mr[1] << 8); 1327 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1328 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1329 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1330 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1331 pdram_timing->mr[1] << 8); 1332 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1333 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1334 pdram_timing->mr[2] << 16); 1335 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1336 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1337 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1338 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1339 pdram_timing->mr[2] << 16); 1340 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1341 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1342 /* PI_156 PI_TFC_F1:RW:16:10 */ 1343 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1344 pdram_timing->tfc_long << 16); 1345 /* PI_162 PI_TWR_F1:RW:8:6 */ 1346 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1347 pdram_timing->twr << 8); 1348 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1349 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1350 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1351 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1352 pdram_timing->trcd << 24); 1353 /* PI_161 PI_TRP_F1:RW:16:8 */ 1354 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1355 pdram_timing->trp << 16); 1356 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1357 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1358 pdram_timing->trtp << 8); 1359 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1360 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1361 pdram_timing->tras_min << 24); 1362 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1363 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1364 pdram_timing->tras_max * 99 / 100); 1365 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1366 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1367 pdram_timing->tmrd << 16); 1368 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1369 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1370 pdram_timing->tdqsck_max); 1371 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1372 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1373 2 * pdram_timing->trefi); 1374 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1375 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1376 20 * pdram_timing->trefi); 1377 } 1378 } 1379 1380 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1381 struct dram_timing_t *pdram_timing, 1382 uint32_t fn) 1383 { 1384 if (fn == 0) 1385 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1386 else 1387 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1388 } 1389 1390 static void gen_rk3399_set_odt(uint32_t odt_en) 1391 { 1392 uint32_t drv_odt_val; 1393 uint32_t i; 1394 1395 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1396 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1397 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1398 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1399 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1400 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1401 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1402 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1403 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1404 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1405 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1406 } 1407 } 1408 1409 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1410 uint32_t index, uint32_t dram_type) 1411 { 1412 uint32_t sw_master_mode = 0; 1413 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1414 uint32_t i; 1415 1416 if (dram_type == DDR3) 1417 total_delay = PI_PAD_DELAY_PS_VALUE; 1418 else if (dram_type == LPDDR3) 1419 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1420 else 1421 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1422 /* total_delay + 0.55tck */ 1423 total_delay += (55 * 10000)/mhz; 1424 rddqs_latency = total_delay * mhz / 1000000; 1425 total_delay -= rddqs_latency * 1000000 / mhz; 1426 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1427 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1428 sw_master_mode = 0xc; 1429 mmio_setbits_32(PHY_REG(ch, 514), 1); 1430 mmio_setbits_32(PHY_REG(ch, 642), 1); 1431 mmio_setbits_32(PHY_REG(ch, 770), 1); 1432 1433 /* setting bypass mode slave delay */ 1434 for (i = 0; i < 4; i++) { 1435 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1436 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1437 0x4a0 << 8); 1438 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1439 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1440 0xa0); 1441 /* rd rddqs_gate delay */ 1442 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1443 rddqs_gate_delay); 1444 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1445 rddqs_latency); 1446 } 1447 for (i = 0; i < 3; i++) 1448 /* adr delay */ 1449 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1450 0x7ff << 16, 0x80 << 16); 1451 1452 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1453 /* 1454 * old status is normal mode, 1455 * and saving the wrdqs slave delay 1456 */ 1457 for (i = 0; i < 4; i++) { 1458 /* save and clear wr dqs slave delay */ 1459 wrdqs_delay_val[ch][index][i] = 0x3ff & 1460 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1461 >> 16); 1462 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1463 0x03ff << 16, 0 << 16); 1464 /* 1465 * in normal mode the cmd may delay 1cycle by 1466 * wrlvl and in bypass mode making dqs also 1467 * delay 1cycle. 1468 */ 1469 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1470 0x07 << 8, 0x1 << 8); 1471 } 1472 } 1473 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1474 /* old status is bypass mode and restore wrlvl resume */ 1475 for (i = 0; i < 4; i++) { 1476 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1477 0x03ff << 16, 1478 (wrdqs_delay_val[ch][index][i] & 1479 0x3ff) << 16); 1480 /* resume phy_write_path_lat_add */ 1481 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1482 } 1483 } 1484 1485 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1486 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1487 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1488 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1489 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1490 1491 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1492 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1493 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1494 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1495 } 1496 1497 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1498 struct drv_odt_lp_config *drv_config, 1499 struct dram_timing_t *pdram_timing, 1500 uint32_t fn) 1501 { 1502 uint32_t tmp, i, div, j; 1503 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1504 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1505 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1506 uint32_t extra_adder, delta, hs_offset; 1507 1508 for (i = 0; i < timing_config->ch_cnt; i++) { 1509 1510 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1511 ie_enable = PI_IE_ENABLE_VALUE; 1512 tsel_enable = PI_TSEL_ENABLE_VALUE; 1513 1514 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1515 1516 /* PHY_LOW_FREQ_SEL */ 1517 /* DENALI_PHY_913 1bit offset_0 */ 1518 if (timing_config->freq > 400) 1519 mmio_clrbits_32(PHY_REG(i, 913), 1); 1520 else 1521 mmio_setbits_32(PHY_REG(i, 913), 1); 1522 1523 /* PHY_RPTR_UPDATE_x */ 1524 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1525 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1526 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1527 tmp++; 1528 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1529 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1530 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1531 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1532 1533 /* PHY_PLL_CTRL */ 1534 /* DENALI_PHY_911 13bits offset_0 */ 1535 /* PHY_LP4_BOOT_PLL_CTRL */ 1536 /* DENALI_PHY_919 13bits offset_0 */ 1537 tmp = (1 << 12) | (2 << 7) | (1 << 1); 1538 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1539 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1540 1541 /* PHY_PLL_CTRL_CA */ 1542 /* DENALI_PHY_911 13bits offset_16 */ 1543 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1544 /* DENALI_PHY_919 13bits offset_16 */ 1545 tmp = (2 << 7) | (1 << 5) | (1 << 1); 1546 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1547 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1548 1549 /* PHY_TCKSRE_WAIT */ 1550 /* DENALI_PHY_922 4bits offset_24 */ 1551 if (pdram_timing->mhz <= 400) 1552 tmp = 1; 1553 else if (pdram_timing->mhz <= 800) 1554 tmp = 3; 1555 else if (pdram_timing->mhz <= 1000) 1556 tmp = 4; 1557 else 1558 tmp = 5; 1559 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1560 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1561 div = pdram_timing->mhz / (2 * 20); 1562 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1563 if (div < j) 1564 break; 1565 } 1566 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1567 1568 if (timing_config->dram_type == DDR3) { 1569 mem_delay_ps = 0; 1570 trpre_min_ps = 1000; 1571 } else if (timing_config->dram_type == LPDDR4) { 1572 mem_delay_ps = 1500; 1573 trpre_min_ps = 900; 1574 } else if (timing_config->dram_type == LPDDR3) { 1575 mem_delay_ps = 2500; 1576 trpre_min_ps = 900; 1577 } else { 1578 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1579 return; 1580 } 1581 total_delay_ps = mem_delay_ps + pad_delay_ps; 1582 delay_frac_ps = 1000 * total_delay_ps / 1583 (1000000 / pdram_timing->mhz); 1584 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1585 gate_delay_frac_ps = gate_delay_ps % 1000; 1586 tmp = gate_delay_frac_ps * 0x200 / 1000; 1587 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1588 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1589 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1590 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1591 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1592 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1593 1594 tmp = gate_delay_ps / 1000; 1595 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1596 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1597 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1598 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1599 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1600 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1601 /* PHY_GTLVL_LAT_ADJ_START */ 1602 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1603 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2; 1604 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1605 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1606 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1607 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1608 1609 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1610 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1611 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1612 rddata_en_ie_dly++; 1613 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1614 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1615 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1616 tsel_adder++; 1617 if (rddata_en_ie_dly > tsel_adder) 1618 extra_adder = rddata_en_ie_dly - tsel_adder; 1619 else 1620 extra_adder = 0; 1621 delta = cas_lat - rddata_en_ie_dly; 1622 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1623 hs_offset = 2; 1624 else 1625 hs_offset = 1; 1626 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1627 tmp = 0; 1628 else if ((delta == 2) || (delta == 1)) 1629 tmp = rddata_en_ie_dly - 0 - extra_adder; 1630 else 1631 tmp = extra_adder; 1632 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1633 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1634 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1635 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1636 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1637 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1638 /* PHY_RDDATA_EN_TSEL_DLY */ 1639 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1640 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1641 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1642 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1643 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1644 1645 if (tsel_adder > rddata_en_ie_dly) 1646 extra_adder = tsel_adder - rddata_en_ie_dly; 1647 else 1648 extra_adder = 0; 1649 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1650 tmp = tsel_adder; 1651 else 1652 tmp = rddata_en_ie_dly - 0 + extra_adder; 1653 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1654 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1655 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1656 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1657 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1658 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1659 /* PHY_RDDATA_EN_DLY */ 1660 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1661 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1662 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1663 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1664 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1665 1666 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1667 /* 1668 * Note:Per-CS Training is not compatible at speeds 1669 * under 533 MHz. If the PHY is running at a speed 1670 * less than 533MHz, all phy_per_cs_training_en_X 1671 * parameters must be cleared to 0. 1672 */ 1673 1674 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1675 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1676 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1677 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1678 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1679 } else { 1680 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1681 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1682 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1683 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1684 } 1685 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1686 timing_config->dram_type); 1687 } 1688 } 1689 1690 static int to_get_clk_index(unsigned int mhz) 1691 { 1692 int pll_cnt, i; 1693 1694 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1695 1696 /* Assumming rate_table is in descending order */ 1697 for (i = 0; i < pll_cnt; i++) { 1698 if (mhz >= dpll_rates_table[i].mhz) 1699 break; 1700 } 1701 1702 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1703 if (i == pll_cnt) 1704 i = pll_cnt - 1; 1705 1706 return i; 1707 } 1708 1709 uint32_t ddr_get_rate(void) 1710 { 1711 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1712 1713 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1714 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1715 postdiv1 = 1716 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1717 postdiv2 = 1718 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1719 1720 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1721 } 1722 1723 /* 1724 * return: bit12: channel 1, external self-refresh 1725 * bit11: channel 1, stdby_mode 1726 * bit10: channel 1, self-refresh with controller and memory clock gate 1727 * bit9: channel 1, self-refresh 1728 * bit8: channel 1, power-down 1729 * 1730 * bit4: channel 1, external self-refresh 1731 * bit3: channel 0, stdby_mode 1732 * bit2: channel 0, self-refresh with controller and memory clock gate 1733 * bit1: channel 0, self-refresh 1734 * bit0: channel 0, power-down 1735 */ 1736 uint32_t exit_low_power(void) 1737 { 1738 uint32_t low_power = 0; 1739 uint32_t channel_mask; 1740 uint32_t tmp, i; 1741 1742 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1743 0x3; 1744 for (i = 0; i < 2; i++) { 1745 if (!(channel_mask & (1 << i))) 1746 continue; 1747 1748 /* exit stdby mode */ 1749 mmio_write_32(CIC_BASE + CIC_CTRL1, 1750 (1 << (i + 16)) | (0 << i)); 1751 /* exit external self-refresh */ 1752 tmp = i ? 12 : 8; 1753 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1754 0x1) << (4 + 8 * i); 1755 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1756 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1757 ; 1758 /* exit auto low-power */ 1759 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1760 /* lp_cmd to exit */ 1761 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1762 0x40) { 1763 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1764 ; 1765 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1766 0x69 << 24); 1767 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1768 0x40) 1769 ; 1770 } 1771 } 1772 return low_power; 1773 } 1774 1775 void resume_low_power(uint32_t low_power) 1776 { 1777 uint32_t channel_mask; 1778 uint32_t tmp, i, val; 1779 1780 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1781 0x3; 1782 for (i = 0; i < 2; i++) { 1783 if (!(channel_mask & (1 << i))) 1784 continue; 1785 1786 /* resume external self-refresh */ 1787 tmp = i ? 12 : 8; 1788 val = (low_power >> (4 + 8 * i)) & 0x1; 1789 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1790 /* resume auto low-power */ 1791 val = (low_power >> (8 * i)) & 0x7; 1792 mmio_setbits_32(CTL_REG(i, 101), val); 1793 /* resume stdby mode */ 1794 val = (low_power >> (3 + 8 * i)) & 0x1; 1795 mmio_write_32(CIC_BASE + CIC_CTRL1, 1796 (1 << (i + 16)) | (val << i)); 1797 } 1798 } 1799 1800 static void dram_low_power_config(void) 1801 { 1802 uint32_t tmp, i; 1803 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1804 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1805 1806 if (dram_type == DDR3) 1807 tmp = (2 << 16) | (0x7 << 8); 1808 else 1809 tmp = (3 << 16) | (0x7 << 8); 1810 1811 for (i = 0; i < ch_cnt; i++) 1812 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1813 1814 /* standby idle */ 1815 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1816 1817 if (ch_cnt == 2) { 1818 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1819 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1820 (0x1<<7)) << 16) | 1821 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1822 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1823 } 1824 1825 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1826 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1827 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1828 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1829 } 1830 1831 void dram_dfs_init(void) 1832 { 1833 uint32_t trefi0, trefi1, boot_freq; 1834 uint32_t rddqs_adjust, rddqs_slave; 1835 1836 /* get sdram config for os reg */ 1837 get_dram_drv_odt_val(sdram_config.dramtype, 1838 &rk3399_dram_status.drv_odt_lp_cfg); 1839 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1840 &sdram_config, 1841 &rk3399_dram_status.drv_odt_lp_cfg); 1842 1843 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1844 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1845 1846 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1847 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1848 rk3399_dram_status.current_index = 1849 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1850 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1851 rk3399_dram_status.index_freq[0] /= 2; 1852 rk3399_dram_status.index_freq[1] /= 2; 1853 } 1854 boot_freq = 1855 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1856 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1857 rk3399_dram_status.boot_freq = boot_freq; 1858 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1859 boot_freq; 1860 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1861 0x1] = 0; 1862 rk3399_dram_status.low_power_stat = 0; 1863 /* 1864 * following register decide if NOC stall the access request 1865 * or return error when NOC being idled. when doing ddr frequency 1866 * scaling in M0 or DCF, we need to make sure noc stall the access 1867 * request, if return error cpu may data abort when ddr frequency 1868 * changing. it don't need to set this register every times, 1869 * so we init this register in function dram_dfs_init(). 1870 */ 1871 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1872 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1873 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1874 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1875 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1876 1877 /* Disable multicast */ 1878 mmio_clrbits_32(PHY_REG(0, 896), 1); 1879 mmio_clrbits_32(PHY_REG(1, 896), 1); 1880 dram_low_power_config(); 1881 1882 /* 1883 * If boot_freq isn't in the bypass mode, it can get the 1884 * rddqs_delay_ps from the result of gate training 1885 */ 1886 if (((mmio_read_32(PHY_REG(0, 86)) >> 8) & 0xf) != 0xc) { 1887 1888 /* 1889 * Select PHY's frequency set to current_index 1890 * index for get the result of gate Training 1891 * from registers 1892 */ 1893 mmio_clrsetbits_32(PHY_REG(0, 896), 0x3 << 8, 1894 rk3399_dram_status.current_index << 8); 1895 rddqs_slave = (mmio_read_32(PHY_REG(0, 77)) >> 16) & 0x3ff; 1896 rddqs_slave = rddqs_slave * 1000000 / boot_freq / 512; 1897 1898 rddqs_adjust = mmio_read_32(PHY_REG(0, 78)) & 0xf; 1899 rddqs_adjust = rddqs_adjust * 1000000 / boot_freq; 1900 rddqs_delay_ps = rddqs_slave + rddqs_adjust - 1901 (1000000 / boot_freq / 2); 1902 } else { 1903 rddqs_delay_ps = 3500; 1904 } 1905 } 1906 1907 /* 1908 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1909 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1910 * arg2: bit0: if odt en 1911 */ 1912 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1913 { 1914 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1915 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1916 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1917 1918 dram_type = rk3399_dram_status.timing_config.dram_type; 1919 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1920 1921 lp_cfg->sr_idle = arg0 & 0xff; 1922 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1923 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1924 lp_cfg->pd_idle = arg1 & 0xfff; 1925 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1926 1927 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1928 1929 exit_low_power(); 1930 1931 *low_power = 0; 1932 1933 /* pd_idle en */ 1934 if (lp_cfg->pd_idle) 1935 *low_power |= ((1 << 0) | (1 << 8)); 1936 /* sr_idle en srpd_lite_idle */ 1937 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1938 *low_power |= ((1 << 1) | (1 << 9)); 1939 /* sr_mc_gate_idle */ 1940 if (lp_cfg->sr_mc_gate_idle) 1941 *low_power |= ((1 << 2) | (1 << 10)); 1942 /* standbyidle */ 1943 if (lp_cfg->standby_idle) { 1944 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1945 *low_power |= ((1 << 3) | (1 << 11)); 1946 else 1947 *low_power |= (1 << 3); 1948 } 1949 1950 pd_tmp = arg1; 1951 if (dram_type != LPDDR4) 1952 pd_tmp = arg1 & 0xfff; 1953 sr_tmp = arg0 & 0xffff; 1954 for (i = 0; i < ch_count; i++) { 1955 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1956 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1957 } 1958 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1959 1960 return 0; 1961 } 1962 1963 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1964 { 1965 /* set PARAM to M0_FUNC_DRAM */ 1966 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); 1967 1968 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1969 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1970 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1971 REFDIV(pll_div.refdiv)); 1972 1973 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1974 1975 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1976 dmbst(); 1977 } 1978 1979 static uint32_t prepare_ddr_timing(uint32_t mhz) 1980 { 1981 uint32_t index; 1982 struct dram_timing_t dram_timing; 1983 1984 rk3399_dram_status.timing_config.freq = mhz; 1985 1986 if (mhz < 300) 1987 rk3399_dram_status.timing_config.dllbp = 1; 1988 else 1989 rk3399_dram_status.timing_config.dllbp = 0; 1990 1991 if (rk3399_dram_status.timing_config.odt == 1) 1992 gen_rk3399_set_odt(1); 1993 1994 index = (rk3399_dram_status.current_index + 1) & 0x1; 1995 1996 /* 1997 * checking if having available gate traiing timing for 1998 * target freq. 1999 */ 2000 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2001 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2002 &dram_timing, index); 2003 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2004 &dram_timing, index); 2005 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2006 &rk3399_dram_status.drv_odt_lp_cfg, 2007 &dram_timing, index); 2008 rk3399_dram_status.index_freq[index] = mhz; 2009 2010 return index; 2011 } 2012 2013 uint32_t ddr_set_rate(uint32_t hz) 2014 { 2015 uint32_t low_power, index, ddr_index; 2016 uint32_t mhz = hz / (1000 * 1000); 2017 2018 if (mhz == 2019 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2020 return mhz; 2021 2022 index = to_get_clk_index(mhz); 2023 mhz = dpll_rates_table[index].mhz; 2024 2025 ddr_index = prepare_ddr_timing(mhz); 2026 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2027 mhz); 2028 if (ddr_index > 1) 2029 goto out; 2030 2031 /* 2032 * Make sure the clock is enabled. The M0 clocks should be on all of the 2033 * time during S0. 2034 */ 2035 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2036 m0_start(); 2037 m0_wait_done(); 2038 m0_stop(); 2039 2040 if (rk3399_dram_status.timing_config.odt == 0) 2041 gen_rk3399_set_odt(0); 2042 2043 rk3399_dram_status.current_index = ddr_index; 2044 low_power = rk3399_dram_status.low_power_stat; 2045 resume_low_power(low_power); 2046 out: 2047 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); 2048 return mhz; 2049 } 2050 2051 uint32_t ddr_round_rate(uint32_t hz) 2052 { 2053 int index; 2054 uint32_t mhz = hz / (1000 * 1000); 2055 2056 index = to_get_clk_index(mhz); 2057 2058 return dpll_rates_table[index].mhz * 1000 * 1000; 2059 } 2060 2061 void ddr_prepare_for_sys_suspend(void) 2062 { 2063 uint32_t mhz = 2064 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2065 2066 /* 2067 * If we're not currently at the boot (assumed highest) frequency, we 2068 * need to change frequencies to configure out current index. 2069 */ 2070 rk3399_suspend_status.freq = mhz; 2071 exit_low_power(); 2072 rk3399_suspend_status.low_power_stat = 2073 rk3399_dram_status.low_power_stat; 2074 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2075 rk3399_dram_status.low_power_stat = 0; 2076 rk3399_dram_status.timing_config.odt = 1; 2077 if (mhz != rk3399_dram_status.boot_freq) 2078 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2079 2080 /* 2081 * This will configure the other index to be the same frequency as the 2082 * current one. We retrain both indices on resume, so both have to be 2083 * setup for the same frequency. 2084 */ 2085 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2086 } 2087 2088 void ddr_prepare_for_sys_resume(void) 2089 { 2090 /* Disable multicast */ 2091 mmio_clrbits_32(PHY_REG(0, 896), 1); 2092 mmio_clrbits_32(PHY_REG(1, 896), 1); 2093 2094 /* The suspend code changes the current index, so reset it now. */ 2095 rk3399_dram_status.current_index = 2096 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2097 rk3399_dram_status.low_power_stat = 2098 rk3399_suspend_status.low_power_stat; 2099 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2100 2101 /* 2102 * Set the saved frequency from suspend if it's different than the 2103 * current frequency. 2104 */ 2105 if (rk3399_suspend_status.freq != 2106 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2107 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2108 return; 2109 } 2110 2111 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2112 resume_low_power(rk3399_dram_status.low_power_stat); 2113 } 2114