1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <debug.h> 7 #include <arch_helpers.h> 8 #include <platform_def.h> 9 #include <plat_private.h> 10 #include <dram.h> 11 #include <pmu_regs.h> 12 #include <rk3399_def.h> 13 #include <secure.h> 14 #include <soc.h> 15 #include <suspend.h> 16 17 #define PMUGRF_OS_REG0 0x300 18 #define PMUGRF_OS_REG1 0x304 19 #define PMUGRF_OS_REG2 0x308 20 #define PMUGRF_OS_REG3 0x30c 21 22 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ 23 ((n) << (8 + (ch) * 4))) 24 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ 25 ((n) << (9 + (ch) * 4))) 26 27 #define FBDIV_ENC(n) ((n) << 16) 28 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) 29 #define POSTDIV2_ENC(n) ((n) << 12) 30 #define POSTDIV2_DEC(n) (((n) >> 12) & 0x7) 31 #define POSTDIV1_ENC(n) ((n) << 8) 32 #define POSTDIV1_DEC(n) (((n) >> 8) & 0x7) 33 #define REFDIV_ENC(n) (n) 34 #define REFDIV_DEC(n) ((n) & 0x3f) 35 36 /* PMU CRU */ 37 #define PMUCRU_RSTNHOLD_CON0 0x120 38 #define PMUCRU_RSTNHOLD_CON1 0x124 39 40 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7)) 41 #define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8)) 42 43 #define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000) 44 45 /* 46 * Copy @num registers from @src to @dst 47 */ 48 static __pmusramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, 49 uint32_t num) 50 { 51 while (num--) { 52 mmio_write_32(dst, mmio_read_32(src)); 53 dst += sizeof(uint32_t); 54 src += sizeof(uint32_t); 55 } 56 } 57 58 /* 59 * Copy @num registers from @src to @dst 60 * This is intentionally a copy of the sram_regcpy function. PMUSRAM functions 61 * cannot be called from code running in DRAM. 62 */ 63 static void dram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num) 64 { 65 while (num--) { 66 mmio_write_32(dst, mmio_read_32(src)); 67 dst += sizeof(uint32_t); 68 src += sizeof(uint32_t); 69 } 70 } 71 72 static __pmusramfunc uint32_t sram_get_timer_value(void) 73 { 74 /* 75 * Generic delay timer implementation expects the timer to be a down 76 * counter. We apply bitwise NOT operator to the tick values returned 77 * by read_cntpct_el0() to simulate the down counter. 78 */ 79 return (uint32_t)(~read_cntpct_el0()); 80 } 81 82 static __pmusramfunc void sram_udelay(uint32_t usec) 83 { 84 uint32_t start, cnt, delta, delta_us; 85 86 /* counter is decreasing */ 87 start = sram_get_timer_value(); 88 do { 89 cnt = sram_get_timer_value(); 90 if (cnt > start) { 91 delta = UINT32_MAX - cnt; 92 delta += start; 93 } else 94 delta = start - cnt; 95 delta_us = (delta * SYS_COUNTER_FREQ_IN_MHZ); 96 } while (delta_us < usec); 97 } 98 99 static __pmusramfunc void configure_sgrf(void) 100 { 101 /* 102 * SGRF_DDR_RGN_DPLL_CLK and SGRF_DDR_RGN_RTC_CLK: 103 * IC ECO bug, need to set this register. 104 * 105 * SGRF_DDR_RGN_BYPS: 106 * After the PD_CENTER suspend/resume, the DDR region 107 * related registers in the SGRF will be reset, we 108 * need to re-initialize them. 109 */ 110 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 111 SGRF_DDR_RGN_DPLL_CLK | 112 SGRF_DDR_RGN_RTC_CLK | 113 SGRF_DDR_RGN_BYPS); 114 } 115 116 static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, 117 uint32_t phy) 118 { 119 channel &= 0x1; 120 ctl &= 0x1; 121 phy &= 0x1; 122 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), 123 CRU_SFTRST_DDR_CTRL(channel, ctl) | 124 CRU_SFTRST_DDR_PHY(channel, phy)); 125 } 126 127 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) 128 { 129 rkclk_ddr_reset(ch, 1, 1); 130 sram_udelay(10); 131 rkclk_ddr_reset(ch, 1, 0); 132 sram_udelay(10); 133 rkclk_ddr_reset(ch, 0, 0); 134 sram_udelay(10); 135 } 136 137 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) 138 { 139 uint32_t byte; 140 141 /* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */ 142 for (byte = 0; byte < 4; byte++) 143 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, 144 rank << 24); 145 } 146 147 static __pmusramfunc void select_per_cs_training_index(uint32_t ch, 148 uint32_t rank) 149 { 150 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ 151 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) 152 set_cs_training_index(ch, rank); 153 } 154 155 static __pmusramfunc void override_write_leveling_value(uint32_t ch) 156 { 157 uint32_t byte; 158 159 for (byte = 0; byte < 4; byte++) { 160 /* 161 * PHY_8/136/264/392 162 * phy_per_cs_training_multicast_en_X 1bit offset_16 163 */ 164 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, 165 1 << 16); 166 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), 167 0xffff << 16, 168 0x200 << 16); 169 } 170 171 /* CTL_200 ctrlupd_req 1bit offset_8 */ 172 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); 173 } 174 175 static __pmusramfunc int data_training(uint32_t ch, 176 struct rk3399_sdram_params *sdram_params, 177 uint32_t training_flag) 178 { 179 uint32_t obs_0, obs_1, obs_2, obs_3, obs_err = 0; 180 uint32_t rank = sdram_params->ch[ch].rank; 181 uint32_t rank_mask; 182 uint32_t i, tmp; 183 184 if (sdram_params->dramtype == LPDDR4) 185 rank_mask = (rank == 1) ? 0x5 : 0xf; 186 else 187 rank_mask = (rank == 1) ? 0x1 : 0x3; 188 189 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 190 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); 191 192 if (training_flag == PI_FULL_TRAINING) { 193 if (sdram_params->dramtype == LPDDR4) { 194 training_flag = PI_WRITE_LEVELING | 195 PI_READ_GATE_TRAINING | 196 PI_READ_LEVELING | 197 PI_WDQ_LEVELING; 198 } else if (sdram_params->dramtype == LPDDR3) { 199 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 200 PI_READ_GATE_TRAINING; 201 } else if (sdram_params->dramtype == DDR3) { 202 training_flag = PI_WRITE_LEVELING | 203 PI_READ_GATE_TRAINING | 204 PI_READ_LEVELING; 205 } 206 } 207 208 /* ca training(LPDDR4,LPDDR3 support) */ 209 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { 210 for (i = 0; i < 4; i++) { 211 if (!(rank_mask & (1 << i))) 212 continue; 213 214 select_per_cs_training_index(ch, i); 215 /* PI_100 PI_CALVL_EN:RW:8:2 */ 216 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); 217 218 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ 219 mmio_clrsetbits_32(PI_REG(ch, 92), 220 (0x1 << 16) | (0x3 << 24), 221 (0x1 << 16) | (i << 24)); 222 while (1) { 223 /* PI_174 PI_INT_STATUS:RD:8:18 */ 224 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 225 226 /* 227 * check status obs 228 * PHY_532/660/788 phy_adr_calvl_obs1_:0:32 229 */ 230 obs_0 = mmio_read_32(PHY_REG(ch, 532)); 231 obs_1 = mmio_read_32(PHY_REG(ch, 660)); 232 obs_2 = mmio_read_32(PHY_REG(ch, 788)); 233 if (((obs_0 >> 30) & 0x3) || 234 ((obs_1 >> 30) & 0x3) || 235 ((obs_2 >> 30) & 0x3)) 236 obs_err = 1; 237 if ((((tmp >> 11) & 0x1) == 0x1) && 238 (((tmp >> 13) & 0x1) == 0x1) && 239 (((tmp >> 5) & 0x1) == 0x0) && 240 (obs_err == 0)) 241 break; 242 else if ((((tmp >> 5) & 0x1) == 0x1) || 243 (obs_err == 1)) 244 return -1; 245 } 246 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 247 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 248 } 249 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); 250 } 251 252 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ 253 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { 254 for (i = 0; i < rank; i++) { 255 select_per_cs_training_index(ch, i); 256 /* PI_60 PI_WRLVL_EN:RW:8:2 */ 257 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); 258 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ 259 mmio_clrsetbits_32(PI_REG(ch, 59), 260 (0x1 << 8) | (0x3 << 16), 261 (0x1 << 8) | (i << 16)); 262 263 while (1) { 264 /* PI_174 PI_INT_STATUS:RD:8:18 */ 265 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 266 267 /* 268 * check status obs, if error maybe can not 269 * get leveling done PHY_40/168/296/424 270 * phy_wrlvl_status_obs_X:0:13 271 */ 272 obs_0 = mmio_read_32(PHY_REG(ch, 40)); 273 obs_1 = mmio_read_32(PHY_REG(ch, 168)); 274 obs_2 = mmio_read_32(PHY_REG(ch, 296)); 275 obs_3 = mmio_read_32(PHY_REG(ch, 424)); 276 if (((obs_0 >> 12) & 0x1) || 277 ((obs_1 >> 12) & 0x1) || 278 ((obs_2 >> 12) & 0x1) || 279 ((obs_3 >> 12) & 0x1)) 280 obs_err = 1; 281 if ((((tmp >> 10) & 0x1) == 0x1) && 282 (((tmp >> 13) & 0x1) == 0x1) && 283 (((tmp >> 4) & 0x1) == 0x0) && 284 (obs_err == 0)) 285 break; 286 else if ((((tmp >> 4) & 0x1) == 0x1) || 287 (obs_err == 1)) 288 return -1; 289 } 290 291 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 292 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 293 } 294 override_write_leveling_value(ch); 295 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); 296 } 297 298 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ 299 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { 300 for (i = 0; i < rank; i++) { 301 select_per_cs_training_index(ch, i); 302 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ 303 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, 304 0x2 << 24); 305 /* 306 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 307 * PI_RDLVL_CS:RW:24:2 308 */ 309 mmio_clrsetbits_32(PI_REG(ch, 74), 310 (0x1 << 16) | (0x3 << 24), 311 (0x1 << 16) | (i << 24)); 312 313 while (1) { 314 /* PI_174 PI_INT_STATUS:RD:8:18 */ 315 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 316 317 /* 318 * check status obs 319 * PHY_43/171/299/427 320 * PHY_GTLVL_STATUS_OBS_x:16:8 321 */ 322 obs_0 = mmio_read_32(PHY_REG(ch, 43)); 323 obs_1 = mmio_read_32(PHY_REG(ch, 171)); 324 obs_2 = mmio_read_32(PHY_REG(ch, 299)); 325 obs_3 = mmio_read_32(PHY_REG(ch, 427)); 326 if (((obs_0 >> (16 + 6)) & 0x3) || 327 ((obs_1 >> (16 + 6)) & 0x3) || 328 ((obs_2 >> (16 + 6)) & 0x3) || 329 ((obs_3 >> (16 + 6)) & 0x3)) 330 obs_err = 1; 331 if ((((tmp >> 9) & 0x1) == 0x1) && 332 (((tmp >> 13) & 0x1) == 0x1) && 333 (((tmp >> 3) & 0x1) == 0x0) && 334 (obs_err == 0)) 335 break; 336 else if ((((tmp >> 3) & 0x1) == 0x1) || 337 (obs_err == 1)) 338 return -1; 339 } 340 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 341 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 342 } 343 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); 344 } 345 346 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ 347 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { 348 for (i = 0; i < rank; i++) { 349 select_per_cs_training_index(ch, i); 350 /* PI_80 PI_RDLVL_EN:RW:16:2 */ 351 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, 352 0x2 << 16); 353 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ 354 mmio_clrsetbits_32(PI_REG(ch, 74), 355 (0x1 << 8) | (0x3 << 24), 356 (0x1 << 8) | (i << 24)); 357 while (1) { 358 /* PI_174 PI_INT_STATUS:RD:8:18 */ 359 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 360 361 /* 362 * make sure status obs not report error bit 363 * PHY_46/174/302/430 364 * phy_rdlvl_status_obs_X:16:8 365 */ 366 if ((((tmp >> 8) & 0x1) == 0x1) && 367 (((tmp >> 13) & 0x1) == 0x1) && 368 (((tmp >> 2) & 0x1) == 0x0)) 369 break; 370 else if (((tmp >> 2) & 0x1) == 0x1) 371 return -1; 372 } 373 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 374 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 375 } 376 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); 377 } 378 379 /* wdq leveling(LPDDR4 support) */ 380 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { 381 for (i = 0; i < 4; i++) { 382 if (!(rank_mask & (1 << i))) 383 continue; 384 385 select_per_cs_training_index(ch, i); 386 /* 387 * disable PI_WDQLVL_VREF_EN before wdq leveling? 388 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 389 */ 390 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); 391 /* PI_124 PI_WDQLVL_EN:RW:16:2 */ 392 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, 393 0x2 << 16); 394 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ 395 mmio_clrsetbits_32(PI_REG(ch, 121), 396 (0x1 << 8) | (0x3 << 16), 397 (0x1 << 8) | (i << 16)); 398 while (1) { 399 /* PI_174 PI_INT_STATUS:RD:8:18 */ 400 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 401 if ((((tmp >> 12) & 0x1) == 0x1) && 402 (((tmp >> 13) & 0x1) == 0x1) && 403 (((tmp >> 6) & 0x1) == 0x0)) 404 break; 405 else if (((tmp >> 6) & 0x1) == 0x1) 406 return -1; 407 } 408 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 409 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 410 } 411 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); 412 } 413 414 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 415 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); 416 417 return 0; 418 } 419 420 static __pmusramfunc void set_ddrconfig( 421 struct rk3399_sdram_params *sdram_params, 422 unsigned char channel, uint32_t ddrconfig) 423 { 424 /* only need to set ddrconfig */ 425 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; 426 unsigned int cs0_cap = 0; 427 unsigned int cs1_cap = 0; 428 429 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20)); 430 if (ch->rank > 1) 431 cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row); 432 if (ch->row_3_4) { 433 cs0_cap = cs0_cap * 3 / 4; 434 cs1_cap = cs1_cap * 3 / 4; 435 } 436 437 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF, 438 ddrconfig | (ddrconfig << 6)); 439 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE, 440 ((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8)); 441 } 442 443 static __pmusramfunc void dram_all_config( 444 struct rk3399_sdram_params *sdram_params) 445 { 446 unsigned int i; 447 448 for (i = 0; i < 2; i++) { 449 struct rk3399_sdram_channel *info = &sdram_params->ch[i]; 450 struct rk3399_msch_timings *noc = &info->noc_timings; 451 452 if (sdram_params->ch[i].col == 0) 453 continue; 454 455 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0, 456 noc->ddrtiminga0.d32); 457 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0, 458 noc->ddrtimingb0.d32); 459 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0, 460 noc->ddrtimingc0.d32); 461 mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0, 462 noc->devtodev0.d32); 463 mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32); 464 465 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ 466 if (sdram_params->ch[i].rank == 1) 467 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); 468 } 469 470 DDR_STRIDE(sdram_params->stride); 471 472 /* reboot hold register set */ 473 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 474 CRU_PMU_SGRF_RST_RLS | 475 PRESET_GPIO0_HOLD(1) | 476 PRESET_GPIO1_HOLD(1)); 477 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); 478 } 479 480 static __pmusramfunc void pctl_cfg(uint32_t ch, 481 struct rk3399_sdram_params *sdram_params) 482 { 483 const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl; 484 const uint32_t *params_pi = sdram_params->pi_regs.denali_pi; 485 const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs; 486 uint32_t tmp, tmp1, tmp2, i; 487 488 /* 489 * Workaround controller bug: 490 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed 491 */ 492 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1], 493 CTL_REG_NUM - 1); 494 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); 495 sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0], 496 PI_REG_NUM); 497 498 sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896], 499 3); 500 501 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, 502 PWRUP_SREFRESH_EXIT); 503 504 /* PHY_DLL_RST_EN */ 505 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24); 506 dmbst(); 507 508 mmio_setbits_32(PI_REG(ch, 0), START); 509 mmio_setbits_32(CTL_REG(ch, 0), START); 510 511 /* wait lock */ 512 while (1) { 513 tmp = mmio_read_32(PHY_REG(ch, 920)); 514 tmp1 = mmio_read_32(PHY_REG(ch, 921)); 515 tmp2 = mmio_read_32(PHY_REG(ch, 922)); 516 if ((((tmp >> 16) & 0x1) == 0x1) && 517 (((tmp1 >> 16) & 0x1) == 0x1) && 518 (((tmp1 >> 0) & 0x1) == 0x1) && 519 (((tmp2 >> 0) & 0x1) == 0x1)) 520 break; 521 /* if PLL bypass,don't need wait lock */ 522 if (mmio_read_32(PHY_REG(ch, 911)) & 0x1) 523 break; 524 } 525 526 sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63); 527 528 for (i = 0; i < 4; i++) 529 sram_regcpy(PHY_REG(ch, 128 * i), 530 (uintptr_t)&phy_regs->phy0[i][0], 91); 531 532 for (i = 0; i < 3; i++) 533 sram_regcpy(PHY_REG(ch, 512 + 128 * i), 534 (uintptr_t)&phy_regs->phy512[i][0], 38); 535 } 536 537 static __pmusramfunc int dram_switch_to_next_index( 538 struct rk3399_sdram_params *sdram_params) 539 { 540 uint32_t ch, ch_count; 541 uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; 542 543 mmio_write_32(CIC_BASE + CIC_CTRL0, 544 (((0x3 << 4) | (1 << 2) | 1) << 16) | 545 (fn << 4) | (1 << 2) | 1); 546 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) 547 ; 548 549 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 550 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0))) 551 ; 552 553 ch_count = sdram_params->num_channels; 554 555 /* LPDDR4 f2 cann't do training, all training will fail */ 556 for (ch = 0; ch < ch_count; ch++) { 557 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, 558 fn << 8); 559 560 /* data_training failed */ 561 if (data_training(ch, sdram_params, PI_FULL_TRAINING)) 562 return -1; 563 } 564 565 return 0; 566 } 567 568 /* 569 * Needs to be done for both channels at once in case of a shared reset signal 570 * between channels. 571 */ 572 static __pmusramfunc int pctl_start(uint32_t channel_mask, 573 struct rk3399_sdram_params *sdram_params) 574 { 575 uint32_t count; 576 uint32_t byte; 577 578 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 579 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 580 581 /* need de-access IO retention before controller START */ 582 if (channel_mask & (1 << 0)) 583 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); 584 if (channel_mask & (1 << 1)) 585 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); 586 587 /* PHY_DLL_RST_EN */ 588 if (channel_mask & (1 << 0)) 589 mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24, 590 0x2 << 24); 591 if (channel_mask & (1 << 1)) 592 mmio_clrsetbits_32(PHY_REG(1, 957), 0x3 << 24, 593 0x2 << 24); 594 595 /* check ERROR bit */ 596 if (channel_mask & (1 << 0)) { 597 count = 0; 598 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { 599 /* CKE is low, loop 10ms */ 600 if (count > 100) 601 return -1; 602 603 sram_udelay(100); 604 count++; 605 } 606 607 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 608 609 /* Restore the PHY_RX_CAL_DQS value */ 610 for (byte = 0; byte < 4; byte++) 611 mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte), 612 0xfff << 16, 613 sdram_params->rx_cal_dqs[0][byte]); 614 } 615 if (channel_mask & (1 << 1)) { 616 count = 0; 617 while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) { 618 /* CKE is low, loop 10ms */ 619 if (count > 100) 620 return -1; 621 622 sram_udelay(100); 623 count++; 624 } 625 626 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 627 628 /* Restore the PHY_RX_CAL_DQS value */ 629 for (byte = 0; byte < 4; byte++) 630 mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte), 631 0xfff << 16, 632 sdram_params->rx_cal_dqs[1][byte]); 633 } 634 635 return 0; 636 } 637 638 void dmc_save(void) 639 { 640 struct rk3399_sdram_params *sdram_params = &sdram_config; 641 struct rk3399_ddr_publ_regs *phy_regs; 642 uint32_t *params_ctl; 643 uint32_t *params_pi; 644 uint32_t refdiv, postdiv2, postdiv1, fbdiv; 645 uint32_t tmp, ch, byte, i; 646 647 phy_regs = &sdram_params->phy_regs; 648 params_ctl = sdram_params->pctl_regs.denali_ctl; 649 params_pi = sdram_params->pi_regs.denali_pi; 650 651 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 652 tmp = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)); 653 postdiv2 = POSTDIV2_DEC(tmp); 654 postdiv1 = POSTDIV1_DEC(tmp); 655 refdiv = REFDIV_DEC(tmp); 656 657 sdram_params->ddr_freq = ((fbdiv * 24) / 658 (refdiv * postdiv1 * postdiv2)) * MHz; 659 660 INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq); 661 sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) & 662 0x7) != 0) ? 1 : 0; 663 664 /* copy the registers CTL PI and PHY */ 665 dram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM); 666 667 /* mask DENALI_CTL_00_DATA.START, only copy here, will trigger later */ 668 params_ctl[0] &= ~(0x1 << 0); 669 670 dram_regcpy((uintptr_t)¶ms_pi[0], PI_REG(0, 0), 671 PI_REG_NUM); 672 673 /* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/ 674 params_pi[0] &= ~(0x1 << 0); 675 676 for (i = 0; i < 4; i++) 677 dram_regcpy((uintptr_t)&phy_regs->phy0[i][0], 678 PHY_REG(0, 128 * i), 91); 679 680 for (i = 0; i < 3; i++) 681 dram_regcpy((uintptr_t)&phy_regs->phy512[i][0], 682 PHY_REG(0, 512 + 128 * i), 38); 683 684 dram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63); 685 686 for (ch = 0; ch < sdram_params->num_channels; ch++) { 687 for (byte = 0; byte < 4; byte++) 688 sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) & 689 mmio_read_32(PHY_REG(ch, 57 + byte * 128)); 690 } 691 692 /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ 693 phy_regs->phy896[957 - 896] &= ~(0x3 << 24); 694 phy_regs->phy896[957 - 896] |= 1 << 24; 695 phy_regs->phy896[0] |= 1; 696 phy_regs->phy896[0] &= ~(0x3 << 8); 697 } 698 699 __pmusramfunc void dmc_restore(void) 700 { 701 struct rk3399_sdram_params *sdram_params = &sdram_config; 702 uint32_t channel_mask = 0; 703 uint32_t channel; 704 705 configure_sgrf(); 706 707 retry: 708 for (channel = 0; channel < sdram_params->num_channels; channel++) { 709 phy_pctrl_reset(channel); 710 pctl_cfg(channel, sdram_params); 711 } 712 713 for (channel = 0; channel < 2; channel++) { 714 if (sdram_params->ch[channel].col) 715 channel_mask |= 1 << channel; 716 } 717 718 if (pctl_start(channel_mask, sdram_params) < 0) 719 goto retry; 720 721 for (channel = 0; channel < sdram_params->num_channels; channel++) { 722 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 723 if (sdram_params->dramtype == LPDDR3) 724 sram_udelay(10); 725 726 /* If traning fail, retry to do it again. */ 727 if (data_training(channel, sdram_params, PI_FULL_TRAINING)) 728 goto retry; 729 730 set_ddrconfig(sdram_params, channel, 731 sdram_params->ch[channel].ddrconfig); 732 } 733 734 dram_all_config(sdram_params); 735 736 /* Switch to index 1 and prepare for DDR frequency switch. */ 737 dram_switch_to_next_index(sdram_params); 738 } 739