1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <gicv2.h> 17 #include <hi3660.h> 18 #include <mmio.h> 19 #include <generic_delay_timer.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 extern unsigned long __COHERENT_RAM_START__; 41 extern unsigned long __COHERENT_RAM_END__; 42 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 53 /* Data structure which holds the extents of the trusted RAM for BL1 */ 54 static meminfo_t bl1_tzram_layout; 55 56 /****************************************************************************** 57 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 58 * interrupts. 59 *****************************************************************************/ 60 const unsigned int g0_interrupt_array[] = { 61 IRQ_SEC_PHY_TIMER, 62 IRQ_SEC_SGI_0 63 }; 64 65 const gicv2_driver_data_t hikey960_gic_data = { 66 .gicd_base = GICD_REG_BASE, 67 .gicc_base = GICC_REG_BASE, 68 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 69 .g0_interrupt_array = g0_interrupt_array, 70 }; 71 72 meminfo_t *bl1_plat_sec_mem_layout(void) 73 { 74 return &bl1_tzram_layout; 75 } 76 77 /* 78 * Perform any BL1 specific platform actions. 79 */ 80 void bl1_early_platform_setup(void) 81 { 82 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 83 unsigned int id, uart_base; 84 85 generic_delay_timer_init(); 86 hikey960_read_boardid(&id); 87 if (id == 5300) 88 uart_base = PL011_UART5_BASE; 89 else 90 uart_base = PL011_UART6_BASE; 91 /* Initialize the console to provide early debug support */ 92 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 93 94 /* Allow BL1 to see the whole Trusted RAM */ 95 bl1_tzram_layout.total_base = BL1_RW_BASE; 96 bl1_tzram_layout.total_size = BL1_RW_SIZE; 97 98 /* Calculate how much RAM BL1 is using and how much remains free */ 99 bl1_tzram_layout.free_base = BL1_RW_BASE; 100 bl1_tzram_layout.free_size = BL1_RW_SIZE; 101 reserve_mem(&bl1_tzram_layout.free_base, 102 &bl1_tzram_layout.free_size, 103 BL1_RAM_BASE, 104 bl1_size); 105 106 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 107 bl1_size); 108 } 109 110 /* 111 * Perform the very early platform specific architecture setup here. At the 112 * moment this only does basic initialization. Later architectural setup 113 * (bl1_arch_setup()) does not do anything platform specific. 114 */ 115 void bl1_plat_arch_setup(void) 116 { 117 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 118 bl1_tzram_layout.total_size, 119 BL1_RO_BASE, 120 BL1_RO_LIMIT, 121 BL1_COHERENT_RAM_BASE, 122 BL1_COHERENT_RAM_LIMIT); 123 } 124 125 static void hikey960_clk_init(void) 126 { 127 /* change ldi0 sel to ppll2 */ 128 mmio_write_32(0xfff350b4, 0xf0002000); 129 /* ldi0 20' */ 130 mmio_write_32(0xfff350bc, 0xfc004c00); 131 } 132 133 static void hikey960_pmu_init(void) 134 { 135 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 136 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 137 } 138 139 static void hikey960_enable_ppll3(void) 140 { 141 /* enable ppll3 */ 142 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 143 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 144 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 145 } 146 147 static void bus_idle_clear(unsigned int value) 148 { 149 unsigned int pmc_value, value1, value2; 150 int timeout = 100; 151 152 pmc_value = value << 16; 153 pmc_value &= ~value; 154 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 155 156 for (;;) { 157 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 158 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 159 if (((value1 & value) == 0) && ((value2 & value) == 0)) 160 break; 161 udelay(1); 162 timeout--; 163 if (timeout <= 0) { 164 WARN("%s timeout\n", __func__); 165 break; 166 } 167 } 168 } 169 170 static void set_vivobus_power_up(void) 171 { 172 /* clk enable */ 173 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 174 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 175 } 176 177 static void set_dss_power_up(void) 178 { 179 /* set edc0 133MHz = 1600MHz / 12 */ 180 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 181 /* set ldi0 ppl0 */ 182 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 183 /* set ldi0 133MHz, 1600MHz / 12 */ 184 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 185 /* mtcmos on */ 186 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 187 udelay(100); 188 /* DISP CRG */ 189 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 190 /* clk enable */ 191 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 192 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 193 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 194 udelay(1); 195 /* clk disable */ 196 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 197 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 198 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 199 udelay(1); 200 /* iso disable */ 201 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 202 /* unreset */ 203 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 204 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 205 /* clk enable */ 206 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 207 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 208 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 209 /* bus idle clear */ 210 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 211 /* set edc0 400MHz for 2K 1600MHz / 4 */ 212 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 213 /* set ldi 266MHz, 1600MHz / 6 */ 214 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 215 } 216 217 static void set_vcodec_power_up(void) 218 { 219 /* clk enable */ 220 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 221 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 222 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 223 /* unreset */ 224 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 225 /* bus idle clear */ 226 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 227 } 228 229 static void set_vdec_power_up(void) 230 { 231 /* mtcmos on */ 232 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 233 udelay(100); 234 /* clk enable */ 235 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 236 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 237 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 238 udelay(1); 239 /* clk disable */ 240 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 241 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 242 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 243 udelay(1); 244 /* iso disable */ 245 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 246 /* unreset */ 247 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 248 /* clk enable */ 249 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 250 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 251 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 252 /* bus idle clear */ 253 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 254 } 255 256 static void set_venc_power_up(void) 257 { 258 /* set venc ppll3 */ 259 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 260 /* set venc 258MHz, 1290MHz / 5 */ 261 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 262 /* mtcmos on */ 263 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 264 udelay(100); 265 /* clk enable */ 266 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 267 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 268 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 269 udelay(1); 270 /* clk disable */ 271 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 272 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 273 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 274 udelay(1); 275 /* iso disable */ 276 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 277 /* unreset */ 278 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 279 /* clk enable */ 280 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 281 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 282 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 283 /* bus idle clear */ 284 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 285 /* set venc 645MHz, 1290MHz / 2 */ 286 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 287 } 288 289 static void set_isp_power_up(void) 290 { 291 /* mtcmos on */ 292 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 293 udelay(100); 294 /* clk enable */ 295 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 296 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 297 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 298 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 299 udelay(1); 300 /* clk disable */ 301 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 302 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 303 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 304 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 305 udelay(1); 306 /* iso disable */ 307 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 308 /* unreset */ 309 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 310 /* clk enable */ 311 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 312 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 313 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 314 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 315 /* bus idle clear */ 316 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 317 /* csi clk enable */ 318 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 319 } 320 321 static void set_ivp_power_up(void) 322 { 323 /* set ivp ppll0 */ 324 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 325 /* set ivp 267MHz, 1600MHz / 6 */ 326 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 327 /* mtcmos on */ 328 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 329 udelay(100); 330 /* IVP CRG unreset */ 331 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 332 /* clk enable */ 333 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 334 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 335 udelay(1); 336 /* clk disable */ 337 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 338 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 339 udelay(1); 340 /* iso disable */ 341 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 342 /* unreset */ 343 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 344 /* clk enable */ 345 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 346 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 347 /* bus idle clear */ 348 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 349 /* set ivp 533MHz, 1600MHz / 3 */ 350 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 351 } 352 353 static void set_audio_power_up(void) 354 { 355 unsigned int ret; 356 int timeout = 100; 357 /* mtcmos on */ 358 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 359 udelay(100); 360 /* clk enable */ 361 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 362 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 363 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 364 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 365 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 366 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 367 udelay(1); 368 /* clk disable */ 369 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 370 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 371 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 372 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 373 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 374 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 375 udelay(1); 376 /* iso disable */ 377 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 378 udelay(1); 379 /* unreset */ 380 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 381 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 382 /* clk enable */ 383 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 384 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 385 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 386 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 387 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 388 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 389 /* bus idle clear */ 390 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 391 for (;;) { 392 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 393 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 394 break; 395 udelay(1); 396 timeout--; 397 if (timeout <= 0) { 398 WARN("%s timeout\n", __func__); 399 break; 400 } 401 } 402 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 403 } 404 405 static void set_pcie_power_up(void) 406 { 407 /* mtcmos on */ 408 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 409 udelay(100); 410 /* clk enable */ 411 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 412 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 413 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 414 udelay(1); 415 /* clk disable */ 416 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 417 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 418 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 419 udelay(1); 420 /* iso disable */ 421 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 422 /* unreset */ 423 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 424 /* clk enable */ 425 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 426 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 427 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 428 } 429 430 static void ispfunc_enable(void) 431 { 432 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 433 mmio_write_32(0xfff35000, 0x00000008); 434 mmio_write_32(0xfff35460, 0xc004ffff); 435 mmio_write_32(0xfff35030, 0x02000000); 436 mdelay(10); 437 } 438 439 static void isps_control_clock(int flag) 440 { 441 unsigned int ret; 442 443 /* flag: 0 -- disable clock, 1 -- enable clock */ 444 if (flag) { 445 ret = mmio_read_32(0xe8420364); 446 ret |= 1; 447 mmio_write_32(0xe8420364, ret); 448 } else { 449 ret = mmio_read_32(0xe8420364); 450 ret &= ~1; 451 mmio_write_32(0xe8420364, ret); 452 } 453 } 454 455 static void set_isp_srt_power_up(void) 456 { 457 unsigned int ret; 458 459 ispfunc_enable(); 460 /* reset */ 461 mmio_write_32(0xe8420374, 0x00000001); 462 mmio_write_32(0xe8420350, 0x00000000); 463 mmio_write_32(0xe8420358, 0x00000000); 464 /* mtcmos on */ 465 mmio_write_32(0xfff35150, 0x00400000); 466 udelay(100); 467 /* clk enable */ 468 isps_control_clock(1); 469 udelay(1); 470 isps_control_clock(0); 471 udelay(1); 472 /* iso disable */ 473 mmio_write_32(0xfff35148, 0x08000000); 474 /* unreset */ 475 ret = mmio_read_32(0xe8420374); 476 ret &= ~0x1; 477 mmio_write_32(0xe8420374, ret); 478 /* clk enable */ 479 isps_control_clock(1); 480 /* enable clock gating for accessing csi registers */ 481 mmio_write_32(0xe8420010, ~0); 482 } 483 484 static void hikey960_regulator_enable(void) 485 { 486 set_vivobus_power_up(); 487 hikey960_enable_ppll3(); 488 set_dss_power_up(); 489 set_vcodec_power_up(); 490 set_vdec_power_up(); 491 set_venc_power_up(); 492 set_isp_power_up(); 493 set_ivp_power_up(); 494 set_audio_power_up(); 495 set_pcie_power_up(); 496 set_isp_srt_power_up(); 497 } 498 499 static void hikey960_ufs_reset(void) 500 { 501 unsigned int data, mask; 502 503 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 504 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 505 do { 506 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 507 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 508 /* use abb clk */ 509 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 510 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 511 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 512 mdelay(1); 513 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 514 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 515 516 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 517 do { 518 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 519 } while ((data & PERI_UFS_BIT) == 0); 520 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 521 mdelay(1); 522 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 523 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 524 MASK_UFS_DEVICE_RESET); 525 /* clear SC_DIV_UFS_PERIBUS */ 526 mask = SC_DIV_UFS_PERIBUS << 16; 527 mmio_write_32(CRG_CLKDIV17_REG, mask); 528 /* set SC_DIV_UFSPHY_CFG(3) */ 529 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 530 data = SC_DIV_UFSPHY_CFG(3); 531 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 532 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 533 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 534 data |= 0x39; 535 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 536 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 537 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 538 MASK_UFS_CLK_GATE_BYPASS); 539 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 540 541 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 542 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 543 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 544 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 545 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 546 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 547 mdelay(1); 548 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 549 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 550 mdelay(20); 551 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 552 0x03300330); 553 554 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 555 do { 556 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 557 } while (data & PERI_UFS_BIT); 558 } 559 560 static void hikey960_ufs_init(void) 561 { 562 dw_ufs_params_t ufs_params; 563 564 memset(&ufs_params, 0, sizeof(ufs_params)); 565 ufs_params.reg_base = UFS_REG_BASE; 566 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 567 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 568 569 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 570 hikey960_ufs_reset(); 571 dw_ufs_init(&ufs_params); 572 } 573 574 static void hikey960_tzc_init(void) 575 { 576 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 577 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 578 mmio_write_32(TZC_EN2_REG, 0x0007005c); 579 mmio_write_32(TZC_EN3_REG, 0x37030700); 580 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 581 mmio_write_32(TZC_EN5_REG, 0x000410fd); 582 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 583 mmio_write_32(TZC_EN7_REG, 0x030000f3); 584 mmio_write_32(TZC_EN8_REG, 0x00000007); 585 } 586 587 static void hikey960_peri_init(void) 588 { 589 /* unreset */ 590 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 591 } 592 593 static void hikey960_pinmux_init(void) 594 { 595 unsigned int id; 596 597 hikey960_read_boardid(&id); 598 if (id == 5301) { 599 /* hikey960 hardware v2 */ 600 /* GPIO150: LED */ 601 mmio_write_32(IOMG_FIX_006_REG, 0); 602 /* GPIO151: LED */ 603 mmio_write_32(IOMG_FIX_007_REG, 0); 604 /* GPIO189: LED */ 605 mmio_write_32(IOMG_AO_011_REG, 0); 606 /* GPIO190: LED */ 607 mmio_write_32(IOMG_AO_012_REG, 0); 608 /* GPIO46 */ 609 mmio_write_32(IOMG_044_REG, 0); 610 /* GPIO202 */ 611 mmio_write_32(IOMG_AO_023_REG, 0); 612 /* GPIO206 */ 613 mmio_write_32(IOMG_AO_026_REG, 0); 614 /* GPIO219 - PD pullup */ 615 mmio_write_32(IOMG_AO_039_REG, 0); 616 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 617 } 618 /* GPIO005 - PMU SSI, 10mA */ 619 mmio_write_32(IOCG_006_REG, 2 << 4); 620 } 621 622 /* 623 * Function which will perform any remaining platform-specific setup that can 624 * occur after the MMU and data cache have been enabled. 625 */ 626 void bl1_platform_setup(void) 627 { 628 hikey960_clk_init(); 629 hikey960_pmu_init(); 630 hikey960_regulator_enable(); 631 hikey960_tzc_init(); 632 hikey960_peri_init(); 633 hikey960_ufs_init(); 634 hikey960_pinmux_init(); 635 hikey960_io_setup(); 636 } 637 638 /* 639 * The following function checks if Firmware update is needed, 640 * by checking if TOC in FIP image is valid or not. 641 */ 642 unsigned int bl1_plat_get_next_image_id(void) 643 { 644 unsigned int mode, ret; 645 646 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 647 switch (mode & BOOT_MODE_MASK) { 648 case BOOT_MODE_RECOVERY: 649 ret = NS_BL1U_IMAGE_ID; 650 break; 651 case BOOT_MODE_NORMAL: 652 ret = BL2_IMAGE_ID; 653 break; 654 default: 655 WARN("Invalid boot mode is found:%d\n", mode); 656 panic(); 657 } 658 return ret; 659 } 660 661 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 662 { 663 unsigned int index = 0; 664 665 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 666 if (bl1_tbbr_image_descs[index].image_id == image_id) 667 return &bl1_tbbr_image_descs[index]; 668 index++; 669 } 670 671 return NULL; 672 } 673 674 void bl1_plat_set_ep_info(unsigned int image_id, 675 entry_point_info_t *ep_info) 676 { 677 unsigned int data = 0; 678 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 679 680 if (image_id == BL2_IMAGE_ID) 681 return; 682 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 683 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 684 NS_BL1U_SIZE); 685 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 686 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 687 /* Initialize the GIC driver, cpu and distributor interfaces */ 688 gicv2_driver_init(&hikey960_gic_data); 689 gicv2_distif_init(); 690 gicv2_pcpu_distif_init(); 691 gicv2_cpuif_enable(); 692 /* CNTFRQ is read-only in EL1 */ 693 write_cntfrq_el0(plat_get_syscnt_freq2()); 694 data = read_cpacr_el1(); 695 do { 696 data |= 3 << 20; 697 write_cpacr_el1(data); 698 data = read_cpacr_el1(); 699 } while ((data & (3 << 20)) != (3 << 20)); 700 INFO("cpacr_el1:0x%x\n", data); 701 702 ep_info->args.arg0 = 0xffff & read_mpidr(); 703 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 704 DISABLE_ALL_EXCEPTIONS); 705 } 706