1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 #ifdef SPD_tspd 83 ARM_MAP_TSP_SEC_MEM, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 #endif 89 #if ARM_BL31_IN_DRAM 90 ARM_MAP_BL31_SEC_DRAM, 91 #endif 92 #ifdef SPD_opteed 93 ARM_MAP_OPTEE_CORE_MEM, 94 ARM_OPTEE_PAGEABLE_LOAD_MEM, 95 #endif 96 {0} 97 }; 98 #endif 99 #ifdef IMAGE_BL2U 100 const mmap_region_t plat_arm_mmap[] = { 101 MAP_DEVICE0, 102 V2M_MAP_IOFPGA, 103 {0} 104 }; 105 #endif 106 #ifdef IMAGE_BL31 107 const mmap_region_t plat_arm_mmap[] = { 108 ARM_MAP_SHARED_RAM, 109 V2M_MAP_IOFPGA, 110 MAP_DEVICE0, 111 MAP_DEVICE1, 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL32 116 const mmap_region_t plat_arm_mmap[] = { 117 #ifdef AARCH32 118 ARM_MAP_SHARED_RAM, 119 #endif 120 V2M_MAP_IOFPGA, 121 MAP_DEVICE0, 122 MAP_DEVICE1, 123 {0} 124 }; 125 #endif 126 127 ARM_CASSERT_MMAP 128 129 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 130 static const int fvp_cci400_map[] = { 131 PLAT_FVP_CCI400_CLUS0_SL_PORT, 132 PLAT_FVP_CCI400_CLUS1_SL_PORT, 133 }; 134 135 static const int fvp_cci5xx_map[] = { 136 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 137 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 138 }; 139 140 static unsigned int get_interconnect_master(void) 141 { 142 unsigned int master; 143 u_register_t mpidr; 144 145 mpidr = read_mpidr_el1(); 146 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 147 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 148 149 assert(master < FVP_CLUSTER_COUNT); 150 return master; 151 } 152 #endif 153 154 /******************************************************************************* 155 * A single boot loader stack is expected to work on both the Foundation FVP 156 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 157 * SYS_ID register provides a mechanism for detecting the differences between 158 * these platforms. This information is stored in a per-BL array to allow the 159 * code to take the correct path.Per BL platform configuration. 160 ******************************************************************************/ 161 void fvp_config_setup(void) 162 { 163 unsigned int rev, hbi, bld, arch, sys_id; 164 165 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 166 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 167 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 168 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 169 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 170 171 if (arch != ARCH_MODEL) { 172 ERROR("This firmware is for FVP models\n"); 173 panic(); 174 } 175 176 /* 177 * The build field in the SYS_ID tells which variant of the GIC 178 * memory is implemented by the model. 179 */ 180 switch (bld) { 181 case BLD_GIC_VE_MMAP: 182 ERROR("Legacy Versatile Express memory map for GIC peripheral" 183 " is not supported\n"); 184 panic(); 185 break; 186 case BLD_GIC_A53A57_MMAP: 187 break; 188 default: 189 ERROR("Unsupported board build %x\n", bld); 190 panic(); 191 } 192 193 /* 194 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 195 * for the Foundation FVP. 196 */ 197 switch (hbi) { 198 case HBI_FOUNDATION_FVP: 199 arm_config.flags = 0; 200 201 /* 202 * Check for supported revisions of Foundation FVP 203 * Allow future revisions to run but emit warning diagnostic 204 */ 205 switch (rev) { 206 case REV_FOUNDATION_FVP_V2_0: 207 case REV_FOUNDATION_FVP_V2_1: 208 case REV_FOUNDATION_FVP_v9_1: 209 case REV_FOUNDATION_FVP_v9_6: 210 break; 211 default: 212 WARN("Unrecognized Foundation FVP revision %x\n", rev); 213 break; 214 } 215 break; 216 case HBI_BASE_FVP: 217 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 218 219 /* 220 * Check for supported revisions 221 * Allow future revisions to run but emit warning diagnostic 222 */ 223 switch (rev) { 224 case REV_BASE_FVP_V0: 225 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 226 break; 227 case REV_BASE_FVP_REVC: 228 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 229 ARM_CONFIG_FVP_HAS_CCI5XX); 230 break; 231 default: 232 WARN("Unrecognized Base FVP revision %x\n", rev); 233 break; 234 } 235 break; 236 default: 237 ERROR("Unsupported board HBI number 0x%x\n", hbi); 238 panic(); 239 } 240 241 /* 242 * We assume that the presence of MT bit, and therefore shifted 243 * affinities, is uniform across the platform: either all CPUs, or no 244 * CPUs implement it. 245 */ 246 if (read_mpidr_el1() & MPIDR_MT_MASK) 247 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 248 } 249 250 251 void fvp_interconnect_init(void) 252 { 253 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 254 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 255 ERROR("Unrecognized CCN variant detected. Only CCN-502" 256 " is supported"); 257 panic(); 258 } 259 260 plat_arm_interconnect_init(); 261 #else 262 uintptr_t cci_base = 0; 263 const int *cci_map = 0; 264 unsigned int map_size = 0; 265 266 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 267 ARM_CONFIG_FVP_HAS_CCI5XX))) { 268 return; 269 } 270 271 /* Initialize the right interconnect */ 272 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 273 cci_base = PLAT_FVP_CCI5XX_BASE; 274 cci_map = fvp_cci5xx_map; 275 map_size = ARRAY_SIZE(fvp_cci5xx_map); 276 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 277 cci_base = PLAT_FVP_CCI400_BASE; 278 cci_map = fvp_cci400_map; 279 map_size = ARRAY_SIZE(fvp_cci400_map); 280 } 281 282 assert(cci_base); 283 assert(cci_map); 284 cci_init(cci_base, cci_map, map_size); 285 #endif 286 } 287 288 void fvp_interconnect_enable(void) 289 { 290 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 291 plat_arm_interconnect_enter_coherency(); 292 #else 293 unsigned int master; 294 295 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 296 ARM_CONFIG_FVP_HAS_CCI5XX)) { 297 master = get_interconnect_master(); 298 cci_enable_snoop_dvm_reqs(master); 299 } 300 #endif 301 } 302 303 void fvp_interconnect_disable(void) 304 { 305 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 306 plat_arm_interconnect_exit_coherency(); 307 #else 308 unsigned int master; 309 310 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 311 ARM_CONFIG_FVP_HAS_CCI5XX)) { 312 master = get_interconnect_master(); 313 cci_disable_snoop_dvm_reqs(master); 314 } 315 #endif 316 } 317