1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CSS_DEF_H__ 8 #define __CSS_DEF_H__ 9 10 #include <arm_def.h> 11 #include <tzc400.h> 12 13 /************************************************************************* 14 * Definitions common to all ARM Compute SubSystems (CSS) 15 *************************************************************************/ 16 #define NSROM_BASE 0x1f000000 17 #define NSROM_SIZE 0x00001000 18 19 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 20 #define CSS_DEVICE_BASE 0x20000000 21 #define CSS_DEVICE_SIZE 0x0e000000 22 23 #define NSRAM_BASE 0x2e000000 24 #define NSRAM_SIZE 0x00008000 25 26 /* System Security Control Registers */ 27 #define SSC_REG_BASE 0x2a420000 28 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 29 30 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 31 #define CSS_NIC400_SLAVE_BOOTSECURE 8 32 33 /* Interrupt handling constants */ 34 #define CSS_IRQ_MHU 69 35 #define CSS_IRQ_GPU_SMMU_0 71 36 #define CSS_IRQ_TZC 80 37 #define CSS_IRQ_TZ_WDOG 86 38 #define CSS_IRQ_SEC_SYS_TIMER 91 39 40 /* MHU register offsets */ 41 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 42 43 /* 44 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 45 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 46 */ 47 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 48 CSS_IRQ_GPU_SMMU_0, \ 49 CSS_IRQ_TZC, \ 50 CSS_IRQ_TZ_WDOG, \ 51 CSS_IRQ_SEC_SYS_TIMER 52 53 #if CSS_USE_SCMI_SDS_DRIVER 54 /* Memory region for shared data storage */ 55 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 56 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 57 /* 58 * The SCMI Channel is placed right after the SDS region 59 */ 60 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 61 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 62 63 /* Trusted mailbox base address common to all CSS */ 64 /* If SDS is present, then mailbox is at top of SRAM */ 65 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 66 67 /* Number of retries for SCP_RAM_READY flag */ 68 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 69 70 #else 71 /* 72 * SCP <=> AP boot configuration 73 * 74 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 75 * the start of the Trusted SRAM. 76 * 77 * Note that the value stored at this address is only valid at boot time, before 78 * the SCP_BL2 image is transferred to SCP. 79 */ 80 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 81 82 /* Trusted mailbox base address common to all CSS */ 83 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 84 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 85 86 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 87 88 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 89 CSS_DEVICE_BASE, \ 90 CSS_DEVICE_SIZE, \ 91 MT_DEVICE | MT_RW | MT_SECURE) 92 93 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 94 NSRAM_BASE, \ 95 NSRAM_SIZE, \ 96 MT_DEVICE | MT_RW | MT_SECURE) 97 98 /* Platform ID address */ 99 #define SSC_VERSION_OFFSET 0x040 100 101 #define SSC_VERSION_CONFIG_SHIFT 28 102 #define SSC_VERSION_MAJOR_REV_SHIFT 24 103 #define SSC_VERSION_MINOR_REV_SHIFT 20 104 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 105 #define SSC_VERSION_PART_NUM_SHIFT 0x0 106 #define SSC_VERSION_CONFIG_MASK 0xf 107 #define SSC_VERSION_MAJOR_REV_MASK 0xf 108 #define SSC_VERSION_MINOR_REV_MASK 0xf 109 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 110 #define SSC_VERSION_PART_NUM_MASK 0xfff 111 112 /* SSC debug configuration registers */ 113 #define SSC_DBGCFG_SET 0x14 114 #define SSC_DBGCFG_CLR 0x18 115 116 #define SPIDEN_INT_CLR_SHIFT 6 117 #define SPIDEN_SEL_SET_SHIFT 7 118 119 #ifndef __ASSEMBLY__ 120 121 /* SSC_VERSION related accessors */ 122 123 /* Returns the part number of the platform */ 124 #define GET_SSC_VERSION_PART_NUM(val) \ 125 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 126 SSC_VERSION_PART_NUM_MASK) 127 128 /* Returns the configuration number of the platform */ 129 #define GET_SSC_VERSION_CONFIG(val) \ 130 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 131 SSC_VERSION_CONFIG_MASK) 132 133 #endif /* __ASSEMBLY__ */ 134 135 /************************************************************************* 136 * Required platform porting definitions common to all 137 * ARM Compute SubSystems (CSS) 138 ************************************************************************/ 139 140 /* 141 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 142 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 143 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 144 * an SCP_BL2/SCP_BL2U image. 145 */ 146 #if CSS_LOAD_SCP_IMAGES 147 148 #if ARM_BL31_IN_DRAM 149 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 150 #endif 151 152 /* 153 * Load address of SCP_BL2 in CSS platform ports 154 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 155 * rw data. Once SCP_BL2 is transferred to the SCP, it is discarded and BL31 156 * is loaded over the top. 157 */ 158 #define SCP_BL2_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 159 #define SCP_BL2_LIMIT BL1_RW_BASE 160 161 #define SCP_BL2U_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 162 #define SCP_BL2U_LIMIT BL1_RW_BASE 163 #endif /* CSS_LOAD_SCP_IMAGES */ 164 165 /* Load address of Non-Secure Image for CSS platform ports */ 166 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 167 168 /* TZC related constants */ 169 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 170 171 /* 172 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 173 * command 174 */ 175 #define CSS_CLUSTER_PWR_STATE_ON 0 176 #define CSS_CLUSTER_PWR_STATE_OFF 3 177 178 #define CSS_CPU_PWR_STATE_ON 1 179 #define CSS_CPU_PWR_STATE_OFF 0 180 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 181 182 #endif /* __CSS_DEF_H__ */ 183