1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <errno.h> 13 #include <generic_delay_timer.h> 14 #include <hi3660.h> 15 #include <mmio.h> 16 #include <platform_def.h> 17 #include <string.h> 18 #include <ufs.h> 19 20 #include "hikey960_def.h" 21 #include "hikey960_private.h" 22 23 /* 24 * The next 2 constants identify the extents of the code & RO data region. 25 * These addresses are used by the MMU setup code and therefore they must be 26 * page-aligned. It is the responsibility of the linker script to ensure that 27 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 28 */ 29 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 30 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 31 32 /* 33 * The next 2 constants identify the extents of the coherent memory region. 34 * These addresses are used by the MMU setup code and therefore they must be 35 * page-aligned. It is the responsibility of the linker script to ensure that 36 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 37 * page-aligned addresses. 38 */ 39 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 40 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 41 42 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 43 44 typedef struct bl2_to_bl31_params_mem { 45 bl31_params_t bl31_params; 46 image_info_t bl31_image_info; 47 image_info_t bl32_image_info; 48 image_info_t bl33_image_info; 49 entry_point_info_t bl33_ep_info; 50 entry_point_info_t bl32_ep_info; 51 entry_point_info_t bl31_ep_info; 52 } bl2_to_bl31_params_mem_t; 53 54 static bl2_to_bl31_params_mem_t bl31_params_mem; 55 56 meminfo_t *bl2_plat_sec_mem_layout(void) 57 { 58 return &bl2_tzram_layout; 59 } 60 61 bl31_params_t *bl2_plat_get_bl31_params(void) 62 { 63 bl31_params_t *bl2_to_bl31_params = NULL; 64 65 /* 66 * Initialise the memory for all the arguments that needs to 67 * be passed to BL3-1 68 */ 69 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 70 71 /* Assign memory for TF related information */ 72 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 73 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 74 75 /* Fill BL3-1 related information */ 76 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 77 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 78 VERSION_1, 0); 79 80 /* Fill BL3-2 related information if it exists */ 81 #if BL32_BASE 82 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 83 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 84 VERSION_1, 0); 85 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 86 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 87 VERSION_1, 0); 88 #endif 89 90 /* Fill BL3-3 related information */ 91 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 92 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 93 PARAM_EP, VERSION_1, 0); 94 95 /* BL3-3 expects to receive the primary CPU MPID (through x0) */ 96 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 97 98 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 99 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 100 VERSION_1, 0); 101 102 return bl2_to_bl31_params; 103 } 104 105 /******************************************************************************* 106 * Populate the extents of memory available for loading SCP_BL2 (if used), 107 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 108 ******************************************************************************/ 109 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 110 { 111 ufs_params_t ufs_params; 112 113 memset(&ufs_params, 0, sizeof(ufs_params_t)); 114 ufs_params.reg_base = UFS_REG_BASE; 115 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 116 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 117 ufs_params.flags = UFS_FLAGS_SKIPINIT; 118 ufs_init(NULL, &ufs_params); 119 120 hikey960_io_setup(); 121 122 *scp_bl2_meminfo = bl2_tzram_layout; 123 } 124 125 extern int load_lpm3(void); 126 127 int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) 128 { 129 int i; 130 int *buf; 131 132 assert(scp_bl2_image_info->image_size < SCP_MEM_SIZE); 133 134 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 135 136 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 137 scp_bl2_image_info->image_base, 138 scp_bl2_image_info->image_size); 139 140 buf = (int *)scp_bl2_image_info->image_base; 141 142 INFO("BL2: SCP_BL2 HEAD:\n"); 143 for (i = 0; i < 64; i += 4) 144 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 145 buf[i], buf[i+1], buf[i+2], buf[i+3]); 146 147 buf = (int *)(scp_bl2_image_info->image_base + 148 scp_bl2_image_info->image_size - 256); 149 150 INFO("BL2: SCP_BL2 TAIL:\n"); 151 for (i = 0; i < 64; i += 4) 152 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 153 buf[i], buf[i+1], buf[i+2], buf[i+3]); 154 155 memcpy((void *)SCP_MEM_BASE, 156 (void *)scp_bl2_image_info->image_base, 157 scp_bl2_image_info->image_size); 158 159 INFO("BL2: SCP_BL2 transferred to SCP\n"); 160 161 load_lpm3(); 162 (void)buf; 163 164 return 0; 165 } 166 167 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 168 { 169 return &bl31_params_mem.bl31_ep_info; 170 } 171 172 void bl2_plat_set_bl31_ep_info(image_info_t *image, 173 entry_point_info_t *bl31_ep_info) 174 { 175 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 176 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 177 DISABLE_ALL_EXCEPTIONS); 178 } 179 180 void bl2_plat_set_bl33_ep_info(image_info_t *image, 181 entry_point_info_t *bl33_ep_info) 182 { 183 unsigned long el_status; 184 unsigned int mode; 185 186 /* Figure out what mode we enter the non-secure world in */ 187 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 188 el_status &= ID_AA64PFR0_ELX_MASK; 189 190 if (el_status) 191 mode = MODE_EL2; 192 else 193 mode = MODE_EL1; 194 195 /* 196 * TODO: Consider the possibility of specifying the SPSR in 197 * the FIP ToC and allowing the platform to have a say as 198 * well. 199 */ 200 bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, 201 DISABLE_ALL_EXCEPTIONS); 202 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 203 } 204 205 void bl2_plat_flush_bl31_params(void) 206 { 207 flush_dcache_range((unsigned long)&bl31_params_mem, 208 sizeof(bl2_to_bl31_params_mem_t)); 209 } 210 211 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 212 { 213 bl33_meminfo->total_base = DDR_BASE; 214 bl33_meminfo->total_size = DDR_SIZE; 215 bl33_meminfo->free_base = DDR_BASE; 216 bl33_meminfo->free_size = DDR_SIZE; 217 } 218 219 void bl2_early_platform_setup(meminfo_t *mem_layout) 220 { 221 unsigned int id, uart_base; 222 223 generic_delay_timer_init(); 224 hikey960_read_boardid(&id); 225 if (id == 5300) 226 uart_base = PL011_UART5_BASE; 227 else 228 uart_base = PL011_UART6_BASE; 229 230 /* Initialize the console to provide early debug support */ 231 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 232 233 /* Setup the BL2 memory layout */ 234 bl2_tzram_layout = *mem_layout; 235 } 236 237 void bl2_plat_arch_setup(void) 238 { 239 hikey960_init_mmu_el1(bl2_tzram_layout.total_base, 240 bl2_tzram_layout.total_size, 241 BL2_RO_BASE, 242 BL2_RO_LIMIT, 243 BL2_COHERENT_RAM_BASE, 244 BL2_COHERENT_RAM_LIMIT); 245 } 246 247 void bl2_platform_setup(void) 248 { 249 /* disable WDT0 */ 250 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 251 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 252 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 253 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 254 } 255 } 256