1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A53_H__ 8 #define __CORTEX_A53_H__ 9 10 /* Cortex-A53 midr for revision 0 */ 11 #define CORTEX_A53_MIDR 0x410FD030 12 13 /* Retention timer tick definitions */ 14 #define RETENTION_ENTRY_TICKS_2 0x1 15 #define RETENTION_ENTRY_TICKS_8 0x2 16 #define RETENTION_ENTRY_TICKS_32 0x3 17 #define RETENTION_ENTRY_TICKS_64 0x4 18 #define RETENTION_ENTRY_TICKS_128 0x5 19 #define RETENTION_ENTRY_TICKS_256 0x6 20 #define RETENTION_ENTRY_TICKS_512 0x7 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A53_ECTLR p15, 1, c15 26 27 #define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) 28 29 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 30 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 31 32 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 33 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 34 35 /******************************************************************************* 36 * CPU Memory Error Syndrome register specific definitions. 37 ******************************************************************************/ 38 #define CORTEX_A53_MERRSR p15, 2, c15 39 40 /******************************************************************************* 41 * CPU Auxiliary Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A53_ACTLR p15, 0, c15 44 45 #define CORTEX_A53_ACTLR_DTAH (1 << 24) 46 47 /******************************************************************************* 48 * L2 Auxiliary Control register specific definitions. 49 ******************************************************************************/ 50 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 51 52 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) 53 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) 54 55 /******************************************************************************* 56 * L2 Extended Control register specific definitions. 57 ******************************************************************************/ 58 #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 59 60 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 61 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) 62 63 /******************************************************************************* 64 * L2 Memory Error Syndrome register specific definitions. 65 ******************************************************************************/ 66 #define CORTEX_A53_L2MERRSR p15, 3, c15 67 68 #endif /* __CORTEX_A53_H__ */ 69