Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-b

Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

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Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which

Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra210: support for secure physical timer

This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <v

Tegra210: support for secure physical timer

This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: SE: add context save support

Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based sa

Tegra210: SE: add context save support

Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based save/restore mechanism
instead.

This patch updates the SE driver to make this change.

Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: per-SoC DRAM base values

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC header

Tegra: per-SoC DRAM base values

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.

Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: restrict non-secure PMC accesses

Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always acc

Tegra: restrict non-secure PMC accesses

Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.

This patch restricts non-secure world access to the PMC block on
such platforms.

Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: skip past sc7entry-fw signature header

This patch skips past the signature header added to the sc7entry-fw
binary by the previous level bootloader. Currently, the size of
the header is 1KB

Tegra210: skip past sc7entry-fw signature header

This patch skips past the signature header added to the sc7entry-fw
binary by the previous level bootloader. Currently, the size of
the header is 1KB, so adjust the start address and the binary size
at the time of copy.

Change-Id: Id0494548009749035846d54df417a960c640c8f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: SiP handlers to allow PMC access

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS worl

Tegra210: SiP handlers to allow PMC access

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

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Tegra210: power off all DMA masters before System Suspend entry

This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no ro

Tegra210: power off all DMA masters before System Suspend entry

This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no rogue agents
in the system trying to over-write the SC7 Entry Firmware with their own.

Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no long

Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: remove support for cluster power down

This patch removes support for powering down a CPU cluster on
Tegra210 platforms as none of them actually use it.

Change-Id: I9665634cf2b5b7b8a1b5a27

Tegra210: remove support for cluster power down

This patch removes support for powering down a CPU cluster on
Tegra210 platforms as none of them actually use it.

Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: support for cluster idle from the CPU

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the clu

Tegra210: support for cluster idle from the CPU

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:

Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
of L1 $ on Cortex-A57 CPUs

Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up

This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.

Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the pla

Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI

Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI because we are not keeping software save
sequence in main.

Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save

Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.

Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>

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Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id:

Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id: Ic196be8fb833dfd04c0e8d460c07058429999613
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra210: se: disable SMMU before suspending SE block

This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU wh

Tegra210: se: disable SMMU before suspending SE block

This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.

Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the ba

Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.

Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: bpmp: power management interface

This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power sta

Tegra210: bpmp: power management interface

This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.

Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210B01: SE1 and SE2/PKA1 context save (atomic)

This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus

Tegra210B01: SE1 and SE2/PKA1 context save (atomic)

This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.

Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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