1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <pmc.h> 19 #include <platform_def.h> 20 #include <security_engine.h> 21 #include <tegra_def.h> 22 #include <tegra_private.h> 23 #include <tegra_platform.h> 24 25 /* 26 * Register used to clear CPU reset signals. Each CPU has two reset 27 * signals: CPU reset (3:0) and Core reset (19:16). 28 */ 29 #define CPU_CMPLX_RESET_CLR 0x454 30 #define CPU_CORE_RESET_MASK 0x10001 31 32 /* Clock and Reset controller registers for system clock's settings */ 33 #define SCLK_RATE 0x30 34 #define SCLK_BURST_POLICY 0x28 35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 36 37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 38 static bool tegra_bpmp_available = true; 39 40 int32_t tegra_soc_validate_power_state(unsigned int power_state, 41 psci_power_state_t *req_state) 42 { 43 int state_id = psci_get_pstate_id(power_state); 44 45 /* Sanity check the requested state id */ 46 switch (state_id) { 47 case PSTATE_ID_CORE_POWERDN: 48 /* 49 * Core powerdown request only for afflvl 0 50 */ 51 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 52 53 break; 54 55 case PSTATE_ID_CLUSTER_IDLE: 56 57 /* 58 * Cluster idle request for afflvl 0 59 */ 60 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 61 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 62 break; 63 64 case PSTATE_ID_SOC_POWERDN: 65 /* 66 * System powerdown request only for afflvl 2 67 */ 68 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 69 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 70 71 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 72 PLAT_SYS_SUSPEND_STATE_ID; 73 74 break; 75 76 default: 77 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 78 return PSCI_E_INVALID_PARAMS; 79 } 80 81 return PSCI_E_SUCCESS; 82 } 83 84 /******************************************************************************* 85 * Platform handler to calculate the proper target power level at the 86 * specified affinity level. 87 ******************************************************************************/ 88 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 89 const plat_local_state_t *states, 90 unsigned int ncpu) 91 { 92 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 93 int cpu = plat_my_core_pos(); 94 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 95 uint32_t bpmp_reply, data[3], val; 96 int ret; 97 98 /* get the power state at this level */ 99 if (lvl == MPIDR_AFFLVL1) 100 target = *(states + core_pos); 101 if (lvl == MPIDR_AFFLVL2) 102 target = *(states + cpu); 103 104 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 105 106 /* initialize the bpmp interface */ 107 ret = tegra_bpmp_init(); 108 if (ret != 0U) { 109 110 /* Cluster idle not allowed */ 111 target = PSCI_LOCAL_STATE_RUN; 112 113 /******************************************* 114 * BPMP is not present, so handle CC6 entry 115 * from the CPU 116 ******************************************/ 117 118 /* check if cluster idle state has been enabled */ 119 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); 120 if (val == ENABLE_CLOSED_LOOP) { 121 /* 122 * flag to indicate that BPMP firmware is not 123 * available and the CPU has to handle entry/exit 124 * for all power states 125 */ 126 tegra_bpmp_available = false; 127 128 /* 129 * Acquire the cluster idle lock to stop 130 * other CPUs from powering up. 131 */ 132 tegra_fc_ccplex_pgexit_lock(); 133 134 /* Cluster idle only from the last standing CPU */ 135 if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { 136 /* Cluster idle allowed */ 137 target = PSTATE_ID_CLUSTER_IDLE; 138 } else { 139 /* release cluster idle lock */ 140 tegra_fc_ccplex_pgexit_unlock(); 141 } 142 } 143 } else { 144 145 /* Cluster power-down */ 146 data[0] = (uint32_t)cpu; 147 data[1] = TEGRA_PM_CC6; 148 data[2] = TEGRA_PM_SC1; 149 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 150 (void *)&data, (int)sizeof(data), 151 (void *)&bpmp_reply, 152 (int)sizeof(bpmp_reply)); 153 154 /* check if cluster power down is allowed */ 155 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 156 157 /* Cluster power down not allowed */ 158 target = PSCI_LOCAL_STATE_RUN; 159 } 160 } 161 162 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 163 (target == PSTATE_ID_SOC_POWERDN)) { 164 165 /* System Suspend */ 166 target = PSTATE_ID_SOC_POWERDN; 167 168 } else { 169 ; /* do nothing */ 170 } 171 172 return target; 173 } 174 175 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 176 { 177 u_register_t mpidr = read_mpidr(); 178 const plat_local_state_t *pwr_domain_state = 179 target_state->pwr_domain_state; 180 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 181 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 182 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 183 uint32_t cfg; 184 int ret = PSCI_E_SUCCESS; 185 uint32_t val; 186 187 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 188 189 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 190 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 191 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 192 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 193 194 if (tegra_chipid_is_t210_b01()) { 195 196 /* Suspend se/se2 and pka1 */ 197 if (tegra_se_suspend() != 0) { 198 ret = PSCI_E_INTERN_FAIL; 199 } 200 } 201 202 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 203 204 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 205 206 if (!tegra_bpmp_available) { 207 208 /* PWM tristate */ 209 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 210 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 211 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 212 val |= PINMUX_PWM_TRISTATE; 213 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 214 } 215 } 216 217 /* Prepare for cluster idle */ 218 tegra_fc_cluster_idle(mpidr); 219 220 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 221 222 /* Prepare for cpu powerdn */ 223 tegra_fc_cpu_powerdn(mpidr); 224 225 } else { 226 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 227 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 228 ret = PSCI_E_NOT_SUPPORTED; 229 } 230 231 return ret; 232 } 233 234 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 235 { 236 u_register_t mpidr = read_mpidr(); 237 const plat_local_state_t *pwr_domain_state = 238 target_state->pwr_domain_state; 239 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 240 241 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 242 243 if (tegra_chipid_is_t210_b01()) { 244 /* Save tzram contents */ 245 tegra_se_save_tzram(); 246 } 247 248 /* enter system suspend */ 249 tegra_fc_soc_powerdn(mpidr); 250 } 251 252 return PSCI_E_SUCCESS; 253 } 254 255 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 256 { 257 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 258 uint32_t cfg; 259 uint32_t val; 260 261 /* platform parameter passed by the previous bootloader */ 262 if (plat_params->l2_ecc_parity_prot_dis != 1) { 263 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 264 val = read_l2ctlr_el1(); 265 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 266 write_l2ctlr_el1(val); 267 } 268 269 /* 270 * Check if we are exiting from SOC_POWERDN. 271 */ 272 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 273 PLAT_SYS_SUSPEND_STATE_ID) { 274 275 /* 276 * Security engine resume 277 */ 278 if (tegra_chipid_is_t210_b01()) { 279 tegra_se_resume(); 280 } 281 282 /* 283 * Lock scratch registers which hold the CPU vectors 284 */ 285 tegra_pmc_lock_cpu_vectors(); 286 287 /* 288 * Enable WRAP to INCR burst type conversions for 289 * incoming requests on the AXI slave ports. 290 */ 291 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 292 val &= ~ENABLE_UNSUP_TX_ERRORS; 293 val |= ENABLE_WRAP_TO_INCR_BURSTS; 294 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 295 296 /* 297 * Restore Boot and Power Management Processor (BPMP) reset 298 * address and reset it. 299 */ 300 if (tegra_bpmp_available) 301 tegra_fc_reset_bpmp(); 302 } 303 304 /* 305 * Check if we are exiting cluster idle state 306 */ 307 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == 308 PSTATE_ID_CLUSTER_IDLE) { 309 310 if (!tegra_bpmp_available) { 311 312 /* PWM un-tristate */ 313 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 314 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 315 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 316 val &= ~PINMUX_PWM_TRISTATE; 317 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 318 } 319 320 /* release cluster idle lock */ 321 tegra_fc_ccplex_pgexit_unlock(); 322 } 323 } 324 325 /* 326 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 327 * used for power management and boot purposes. Inform the BPMP that 328 * we have completed the cluster power up. 329 */ 330 tegra_fc_lock_active_cluster(); 331 332 return PSCI_E_SUCCESS; 333 } 334 335 int tegra_soc_pwr_domain_on(u_register_t mpidr) 336 { 337 int cpu = mpidr & MPIDR_CPU_MASK; 338 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 339 340 /* Deassert CPU reset signals */ 341 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 342 343 /* Turn on CPU using flow controller or PMC */ 344 if (cpu_powergate_mask[cpu] == 0) { 345 tegra_pmc_cpu_on(cpu); 346 cpu_powergate_mask[cpu] = 1; 347 } else { 348 tegra_fc_cpu_on(cpu); 349 } 350 351 return PSCI_E_SUCCESS; 352 } 353 354 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 355 { 356 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 357 return PSCI_E_SUCCESS; 358 } 359 360 int tegra_soc_prepare_system_reset(void) 361 { 362 /* 363 * Set System Clock (SCLK) to POR default so that the clock source 364 * for the PMC APB clock would not be changed due to system reset. 365 */ 366 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 367 SCLK_BURST_POLICY_DEFAULT); 368 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 369 370 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 371 mdelay(1); 372 373 return PSCI_E_SUCCESS; 374 } 375