1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <pmc.h> 19 #include <platform_def.h> 20 #include <security_engine.h> 21 #include <tegra_def.h> 22 #include <tegra_private.h> 23 #include <tegra_platform.h> 24 #include <utils.h> 25 26 /* 27 * Register used to clear CPU reset signals. Each CPU has two reset 28 * signals: CPU reset (3:0) and Core reset (19:16). 29 */ 30 #define CPU_CMPLX_RESET_CLR 0x454 31 #define CPU_CORE_RESET_MASK 0x10001 32 33 /* Clock and Reset controller registers for system clock's settings */ 34 #define SCLK_RATE 0x30 35 #define SCLK_BURST_POLICY 0x28 36 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 37 38 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 39 static bool tegra_bpmp_available = true; 40 41 int32_t tegra_soc_validate_power_state(unsigned int power_state, 42 psci_power_state_t *req_state) 43 { 44 int state_id = psci_get_pstate_id(power_state); 45 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 46 47 /* Sanity check the requested state id */ 48 switch (state_id) { 49 case PSTATE_ID_CORE_POWERDN: 50 /* 51 * Core powerdown request only for afflvl 0 52 */ 53 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 54 55 break; 56 57 case PSTATE_ID_CLUSTER_IDLE: 58 59 /* 60 * Cluster idle request for afflvl 0 61 */ 62 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 63 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 64 break; 65 66 case PSTATE_ID_SOC_POWERDN: 67 68 /* 69 * sc7entry-fw must be present in the system when the bpmp 70 * firmware is not present, for a successful System Suspend 71 * entry. 72 */ 73 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) 74 return PSCI_E_NOT_SUPPORTED; 75 76 /* 77 * System powerdown request only for afflvl 2 78 */ 79 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 80 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 81 82 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 83 PLAT_SYS_SUSPEND_STATE_ID; 84 85 break; 86 87 default: 88 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 89 return PSCI_E_INVALID_PARAMS; 90 } 91 92 return PSCI_E_SUCCESS; 93 } 94 95 /******************************************************************************* 96 * Platform handler to calculate the proper target power level at the 97 * specified affinity level. 98 ******************************************************************************/ 99 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 100 const plat_local_state_t *states, 101 unsigned int ncpu) 102 { 103 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 104 int cpu = plat_my_core_pos(); 105 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 106 uint32_t bpmp_reply, data[3], val; 107 int ret; 108 109 /* get the power state at this level */ 110 if (lvl == MPIDR_AFFLVL1) 111 target = *(states + core_pos); 112 if (lvl == MPIDR_AFFLVL2) 113 target = *(states + cpu); 114 115 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 116 117 /* initialize the bpmp interface */ 118 ret = tegra_bpmp_init(); 119 if (ret != 0U) { 120 121 /* Cluster idle not allowed */ 122 target = PSCI_LOCAL_STATE_RUN; 123 124 /******************************************* 125 * BPMP is not present, so handle CC6 entry 126 * from the CPU 127 ******************************************/ 128 129 /* check if cluster idle state has been enabled */ 130 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); 131 if (val == ENABLE_CLOSED_LOOP) { 132 /* 133 * flag to indicate that BPMP firmware is not 134 * available and the CPU has to handle entry/exit 135 * for all power states 136 */ 137 tegra_bpmp_available = false; 138 139 /* 140 * Acquire the cluster idle lock to stop 141 * other CPUs from powering up. 142 */ 143 tegra_fc_ccplex_pgexit_lock(); 144 145 /* Cluster idle only from the last standing CPU */ 146 if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { 147 /* Cluster idle allowed */ 148 target = PSTATE_ID_CLUSTER_IDLE; 149 } else { 150 /* release cluster idle lock */ 151 tegra_fc_ccplex_pgexit_unlock(); 152 } 153 } 154 } else { 155 156 /* Cluster power-down */ 157 data[0] = (uint32_t)cpu; 158 data[1] = TEGRA_PM_CC6; 159 data[2] = TEGRA_PM_SC1; 160 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 161 (void *)&data, (int)sizeof(data), 162 (void *)&bpmp_reply, 163 (int)sizeof(bpmp_reply)); 164 165 /* check if cluster power down is allowed */ 166 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 167 168 /* Cluster power down not allowed */ 169 target = PSCI_LOCAL_STATE_RUN; 170 } 171 } 172 173 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 174 (target == PSTATE_ID_SOC_POWERDN)) { 175 176 /* System Suspend */ 177 target = PSTATE_ID_SOC_POWERDN; 178 179 } else { 180 ; /* do nothing */ 181 } 182 183 return target; 184 } 185 186 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 187 { 188 u_register_t mpidr = read_mpidr(); 189 const plat_local_state_t *pwr_domain_state = 190 target_state->pwr_domain_state; 191 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 192 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 193 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 194 uint32_t cfg; 195 int ret = PSCI_E_SUCCESS; 196 uint32_t val; 197 198 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 199 200 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 201 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 202 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 203 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 204 205 if (tegra_chipid_is_t210_b01()) { 206 207 /* Suspend se/se2 and pka1 */ 208 if (tegra_se_suspend() != 0) { 209 ret = PSCI_E_INTERN_FAIL; 210 } 211 } 212 213 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 214 215 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 216 217 if (!tegra_bpmp_available) { 218 219 /* Find if the platform uses OVR2/MAX77621 PMIC */ 220 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 221 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 222 /* OVR2 */ 223 224 /* PWM tristate */ 225 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 226 val |= PINMUX_PWM_TRISTATE; 227 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 228 229 /* 230 * SCRATCH201[1] is being used to identify CPU 231 * PMIC in warmboot code. 232 * 0 : OVR2 233 * 1 : MAX77621 234 */ 235 tegra_pmc_write_32(PMC_SCRATCH201, 0x0); 236 } else { 237 /* MAX77621 */ 238 tegra_pmc_write_32(PMC_SCRATCH201, 0x2); 239 } 240 } 241 242 /* Prepare for cluster idle */ 243 tegra_fc_cluster_idle(mpidr); 244 245 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 246 247 /* Prepare for cpu powerdn */ 248 tegra_fc_cpu_powerdn(mpidr); 249 250 } else { 251 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 252 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 253 ret = PSCI_E_NOT_SUPPORTED; 254 } 255 256 return ret; 257 } 258 259 static void tegra_reset_all_dma_masters(void) 260 { 261 uint32_t val, mask; 262 263 /* 264 * Reset all possible DMA masters in the system. 265 */ 266 val = GPU_RESET_BIT; 267 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val); 268 269 val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | 270 NVJPG_RESET_BIT | NVDEC_RESET_BIT; 271 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val); 272 273 val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | 274 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | 275 SDMMC2_RESET_BIT; 276 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val); 277 278 val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; 279 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val); 280 281 val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | 282 PCIE_RESET_BIT | SDMMC3_RESET_BIT; 283 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val); 284 285 val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; 286 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val); 287 288 /* 289 * If any of the DMA masters are still alive, assume 290 * that the system has been compromised and reboot. 291 */ 292 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); 293 mask = GPU_RESET_BIT; 294 if ((val & mask) != mask) 295 tegra_pmc_system_reset(); 296 297 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | 298 NVJPG_RESET_BIT | NVDEC_RESET_BIT; 299 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y); 300 if ((val & mask) != mask) 301 tegra_pmc_system_reset(); 302 303 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | 304 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | 305 SDMMC2_RESET_BIT; 306 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L); 307 if ((val & mask) != mask) 308 tegra_pmc_system_reset(); 309 310 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; 311 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H); 312 if ((val & mask) != mask) 313 tegra_pmc_system_reset(); 314 315 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | 316 PCIE_RESET_BIT | SDMMC3_RESET_BIT; 317 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U); 318 if ((val & mask) != mask) 319 tegra_pmc_system_reset(); 320 321 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V); 322 mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; 323 if ((val & mask) != mask) 324 tegra_pmc_system_reset(); 325 } 326 327 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 328 { 329 u_register_t mpidr = read_mpidr(); 330 const plat_local_state_t *pwr_domain_state = 331 target_state->pwr_domain_state; 332 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 333 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 334 uint32_t val; 335 336 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 337 338 if (tegra_chipid_is_t210_b01()) { 339 /* Save tzram contents */ 340 tegra_se_save_tzram(); 341 } 342 343 /* 344 * The CPU needs to load the System suspend entry firmware 345 * if nothing is running on the BPMP. 346 */ 347 if (!tegra_bpmp_available) { 348 349 /* 350 * BPMP firmware is not running on the co-processor, so 351 * we need to explicitly load the firmware to enable 352 * entry/exit to/from System Suspend and set the BPMP 353 * on its way. 354 */ 355 356 /* Power off BPMP before we proceed */ 357 tegra_fc_bpmp_off(); 358 359 /* bond out IRAM banks B, C and D */ 360 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U, 361 IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT | 362 IRAM_D_LOCK_BIT); 363 364 /* bond out APB/AHB DMAs */ 365 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H, 366 APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT); 367 368 /* Power off BPMP before we proceed */ 369 tegra_fc_bpmp_off(); 370 371 /* 372 * Reset all the hardware blocks that can act as DMA 373 * masters on the bus. 374 */ 375 tegra_reset_all_dma_masters(); 376 377 /* clean up IRAM of any cruft */ 378 zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE, 379 TEGRA_IRAM_A_SIZE); 380 381 /* Copy the firmware to BPMP's internal RAM */ 382 (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE, 383 (const void *)plat_params->sc7entry_fw_base, 384 plat_params->sc7entry_fw_size); 385 386 /* Power on the BPMP and execute from IRAM base */ 387 tegra_fc_bpmp_on(TEGRA_IRAM_BASE); 388 389 /* Wait until BPMP powers up */ 390 do { 391 val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET); 392 } while (val != SIGN_OF_LIFE); 393 } 394 395 /* enter system suspend */ 396 tegra_fc_soc_powerdn(mpidr); 397 } 398 399 return PSCI_E_SUCCESS; 400 } 401 402 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 403 { 404 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 405 uint32_t cfg; 406 uint32_t val, entrypoint = 0; 407 408 /* platform parameter passed by the previous bootloader */ 409 if (plat_params->l2_ecc_parity_prot_dis != 1) { 410 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 411 val = read_l2ctlr_el1(); 412 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 413 write_l2ctlr_el1(val); 414 } 415 416 /* 417 * Check if we are exiting from SOC_POWERDN. 418 */ 419 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 420 PLAT_SYS_SUSPEND_STATE_ID) { 421 422 /* 423 * Security engine resume 424 */ 425 if (tegra_chipid_is_t210_b01()) { 426 tegra_se_resume(); 427 } 428 429 /* 430 * Lock scratch registers which hold the CPU vectors 431 */ 432 tegra_pmc_lock_cpu_vectors(); 433 434 /* 435 * Enable WRAP to INCR burst type conversions for 436 * incoming requests on the AXI slave ports. 437 */ 438 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 439 val &= ~ENABLE_UNSUP_TX_ERRORS; 440 val |= ENABLE_WRAP_TO_INCR_BURSTS; 441 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 442 443 /* 444 * Restore Boot and Power Management Processor (BPMP) reset 445 * address and reset it, if it is supported by the platform. 446 */ 447 if (!tegra_bpmp_available) { 448 tegra_fc_bpmp_off(); 449 } else { 450 entrypoint = tegra_pmc_read_32(PMC_SCRATCH39); 451 tegra_fc_bpmp_on(entrypoint); 452 } 453 } 454 455 /* 456 * Check if we are exiting cluster idle state 457 */ 458 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == 459 PSTATE_ID_CLUSTER_IDLE) { 460 461 if (!tegra_bpmp_available) { 462 463 /* PWM un-tristate */ 464 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 465 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 466 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 467 val &= ~PINMUX_PWM_TRISTATE; 468 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 469 } 470 471 /* release cluster idle lock */ 472 tegra_fc_ccplex_pgexit_unlock(); 473 } 474 } 475 476 /* 477 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 478 * used for power management and boot purposes. Inform the BPMP that 479 * we have completed the cluster power up. 480 */ 481 tegra_fc_lock_active_cluster(); 482 483 return PSCI_E_SUCCESS; 484 } 485 486 int tegra_soc_pwr_domain_on(u_register_t mpidr) 487 { 488 int cpu = mpidr & MPIDR_CPU_MASK; 489 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 490 491 /* Deassert CPU reset signals */ 492 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 493 494 /* Turn on CPU using flow controller or PMC */ 495 if (cpu_powergate_mask[cpu] == 0) { 496 tegra_pmc_cpu_on(cpu); 497 cpu_powergate_mask[cpu] = 1; 498 } else { 499 tegra_fc_cpu_on(cpu); 500 } 501 502 return PSCI_E_SUCCESS; 503 } 504 505 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 506 { 507 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 508 return PSCI_E_SUCCESS; 509 } 510 511 int tegra_soc_prepare_system_reset(void) 512 { 513 /* 514 * Set System Clock (SCLK) to POR default so that the clock source 515 * for the PMC APB clock would not be changed due to system reset. 516 */ 517 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 518 SCLK_BURST_POLICY_DEFAULT); 519 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 520 521 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 522 mdelay(1); 523 524 return PSCI_E_SUCCESS; 525 } 526