xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/t210/tegra_def.h (revision 93e3b0f34b4e1e2635f1806ada7cd0d71e7b6a87) 
1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef TEGRA_DEF_H
8 #define TEGRA_DEF_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * Power down state IDs
14  ******************************************************************************/
15 #define PSTATE_ID_CORE_POWERDN		U(7)
16 #define PSTATE_ID_CLUSTER_IDLE		U(16)
17 #define PSTATE_ID_SOC_POWERDN		U(27)
18 
19 /*******************************************************************************
20  * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
21  * call as the `state-id` field in the 'power state' parameter.
22  ******************************************************************************/
23 #define PLAT_SYS_SUSPEND_STATE_ID	PSTATE_ID_SOC_POWERDN
24 
25 /*******************************************************************************
26  * Platform power states (used by PSCI framework)
27  *
28  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
29  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
30  ******************************************************************************/
31 #define PLAT_MAX_RET_STATE		U(1)
32 #define PLAT_MAX_OFF_STATE		(PSTATE_ID_SOC_POWERDN + U(1))
33 
34 /*******************************************************************************
35  * Chip specific page table and MMU setup constants
36  ******************************************************************************/
37 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 35)
38 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 35)
39 
40 /*******************************************************************************
41  * iRAM memory constants
42  ******************************************************************************/
43 #define TEGRA_IRAM_BASE			0x40000000
44 
45 /*******************************************************************************
46  * GIC memory map
47  ******************************************************************************/
48 #define TEGRA_GICD_BASE			U(0x50041000)
49 #define TEGRA_GICC_BASE			U(0x50042000)
50 
51 /*******************************************************************************
52  * Secure IRQ definitions
53  ******************************************************************************/
54 #define TEGRA210_WDT_CPU_LEGACY_FIQ		U(28)
55 
56 /*******************************************************************************
57  * Tegra Memory Select Switch Controller constants
58  ******************************************************************************/
59 #define TEGRA_MSELECT_BASE		U(0x50060000)
60 
61 #define MSELECT_CONFIG			U(0x0)
62 #define ENABLE_WRAP_INCR_MASTER2_BIT	(U(1) << U(29))
63 #define ENABLE_WRAP_INCR_MASTER1_BIT	(U(1) << U(28))
64 #define ENABLE_WRAP_INCR_MASTER0_BIT	(U(1) << U(27))
65 #define UNSUPPORTED_TX_ERR_MASTER2_BIT	(U(1) << U(25))
66 #define UNSUPPORTED_TX_ERR_MASTER1_BIT	(U(1) << U(24))
67 #define ENABLE_UNSUP_TX_ERRORS		(UNSUPPORTED_TX_ERR_MASTER2_BIT | \
68 					 UNSUPPORTED_TX_ERR_MASTER1_BIT)
69 #define ENABLE_WRAP_TO_INCR_BURSTS	(ENABLE_WRAP_INCR_MASTER2_BIT | \
70 					 ENABLE_WRAP_INCR_MASTER1_BIT | \
71 					 ENABLE_WRAP_INCR_MASTER0_BIT)
72 
73 /*******************************************************************************
74  * Tegra Resource Semaphore constants
75  ******************************************************************************/
76 #define TEGRA_RES_SEMA_BASE		0x60001000UL
77 #define  STA_OFFSET			0UL
78 #define  SET_OFFSET			4UL
79 #define  CLR_OFFSET			8UL
80 
81 /*******************************************************************************
82  * Tegra Primary Interrupt Controller constants
83  ******************************************************************************/
84 #define TEGRA_PRI_ICTLR_BASE		0x60004000UL
85 #define  CPU_IEP_FIR_SET		0x18UL
86 
87 /*******************************************************************************
88  * Tegra micro-seconds timer constants
89  ******************************************************************************/
90 #define TEGRA_TMRUS_BASE		U(0x60005010)
91 #define TEGRA_TMRUS_SIZE		U(0x1000)
92 
93 /*******************************************************************************
94  * Tegra Clock and Reset Controller constants
95  ******************************************************************************/
96 #define TEGRA_CAR_RESET_BASE		U(0x60006000)
97 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x28C)
98 #define TEGRA_GPU_RESET_GPU_SET_OFFSET	U(0x290)
99 #define  GPU_RESET_BIT			(U(1) << 24)
100 #define  GPU_SET_BIT			(U(1) << 24)
101 #define TEGRA_RST_DEV_CLR_V		U(0x434)
102 #define TEGRA_CLK_ENB_V			U(0x440)
103 
104 /* SE Clock Offsets */
105 #define TEGRA_RST_DEVICES_V		0x358UL
106 #define  SE_RESET_BIT 			(0x1UL << 31)
107 #define TEGRA_RST_DEVICES_W		 0x35CUL
108 #define  ENTROPY_CLK_ENB_BIT		(0x1UL << 21)
109 #define TEGRA_CLK_OUT_ENB_V		0x360UL
110 #define  SE_CLK_ENB_BIT			(0x1UL << 31)
111 #define TEGRA_CLK_OUT_ENB_W		0x364UL
112 #define  ENTROPY_RESET_BIT 		(0x1UL << 21)
113 
114 /*******************************************************************************
115  * Tegra Flow Controller constants
116  ******************************************************************************/
117 #define TEGRA_FLOWCTRL_BASE		U(0x60007000)
118 
119 /*******************************************************************************
120  * Tegra AHB arbitration controller
121  ******************************************************************************/
122 #define TEGRA_AHB_ARB_BASE		0x6000C000UL
123 
124 /*******************************************************************************
125  * Tegra Secure Boot Controller constants
126  ******************************************************************************/
127 #define TEGRA_SB_BASE			U(0x6000C200)
128 
129 /*******************************************************************************
130  * Tegra Exception Vectors constants
131  ******************************************************************************/
132 #define TEGRA_EVP_BASE			U(0x6000F000)
133 
134 /*******************************************************************************
135  * Tegra Miscellaneous register constants
136  ******************************************************************************/
137 #define TEGRA_MISC_BASE			U(0x70000000)
138 #define  HARDWARE_REVISION_OFFSET	U(0x804)
139 #define  PINMUX_AUX_DVFS_PWM		U(0x3184)
140 #define  PINMUX_PWM_TRISTATE		(U(1) << 4)
141 
142 /*******************************************************************************
143  * Tegra UART controller base addresses
144  ******************************************************************************/
145 #define TEGRA_UARTA_BASE		U(0x70006000)
146 #define TEGRA_UARTB_BASE		U(0x70006040)
147 #define TEGRA_UARTC_BASE		U(0x70006200)
148 #define TEGRA_UARTD_BASE		U(0x70006300)
149 #define TEGRA_UARTE_BASE		U(0x70006400)
150 
151 /*******************************************************************************
152  * Tegra Fuse Controller related constants
153  ******************************************************************************/
154 #define TEGRA_FUSE_BASE			0x7000F800UL
155 #define FUSE_BOOT_SECURITY_INFO		0x268UL
156 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN	(0x1U << 7)
157 #define FUSE_JTAG_SECUREID_VALID	(0x104UL)
158 #define ECID_VALID			(0x1UL)
159 
160 
161 /*******************************************************************************
162  * Tegra Power Mgmt Controller constants
163  ******************************************************************************/
164 #define TEGRA_PMC_BASE			U(0x7000E400)
165 
166 /*******************************************************************************
167  * Tegra Atomics constants
168  ******************************************************************************/
169 #define TEGRA_ATOMICS_BASE		0x70016000UL
170 #define  TRIGGER0_REG_OFFSET		0UL
171 #define  TRIGGER_WIDTH_SHIFT		4UL
172 #define  TRIGGER_ID_SHIFT		16UL
173 #define  RESULT0_REG_OFFSET		0xC00UL
174 
175 /*******************************************************************************
176  * Tegra Memory Controller constants
177  ******************************************************************************/
178 #define TEGRA_MC_BASE			U(0x70019000)
179 
180 /* Memory Controller Interrupt Status */
181 #define MC_INTSTATUS			0x00U
182 
183 /* TZDRAM carveout configuration registers */
184 #define MC_SECURITY_CFG0_0		U(0x70)
185 #define MC_SECURITY_CFG1_0		U(0x74)
186 #define MC_SECURITY_CFG3_0		U(0x9BC)
187 
188 /* Video Memory carveout configuration registers */
189 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
190 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
191 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
192 
193 /* SMMU configuration registers*/
194 #define MC_SMMU_PPCS_ASID_0		0x270U
195 #define  PPCS_SMMU_ENABLE		(0x1U << 31)
196 
197 /*******************************************************************************
198  * Tegra CLDVFS constants
199  ******************************************************************************/
200 #define TEGRA_CL_DVFS_BASE		U(0x70110000)
201 #define DVFS_DFLL_CTRL			U(0x00)
202 #define  ENABLE_OPEN_LOOP		U(1)
203 #define  ENABLE_CLOSED_LOOP		U(2)
204 #define DVFS_DFLL_OUTPUT_CFG		U(0x20)
205 #define  DFLL_OUTPUT_CFG_I2C_EN_BIT	(U(1) << 30)
206 #define  DFLL_OUTPUT_CFG_CLK_EN_BIT	(U(1) << 6)
207 
208 /*******************************************************************************
209  * Tegra SE constants
210  ******************************************************************************/
211 #define TEGRA_SE1_BASE			U(0x70012000)
212 #define TEGRA_SE2_BASE			U(0x70412000)
213 #define TEGRA_PKA1_BASE			U(0x70420000)
214 #define TEGRA_SE2_RANGE_SIZE		U(0x2000)
215 #define SE_TZRAM_SECURITY		U(0x4)
216 
217 /*******************************************************************************
218  * Tegra TZRAM constants
219  ******************************************************************************/
220 #define TEGRA_TZRAM_BASE		U(0x7C010000)
221 #define TEGRA_TZRAM_SIZE		U(0x10000)
222 
223 /*******************************************************************************
224  * Tegra TZRAM carveout constants
225  ******************************************************************************/
226 #define TEGRA_TZRAM_CARVEOUT_BASE	U(0x7C04C000)
227 #define TEGRA_TZRAM_CARVEOUT_SIZE	U(0x4000)
228 
229 #endif /* TEGRA_DEF_H */
230