1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_CLUSTER_POWERDN U(17) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * iRAM memory constants 37 ******************************************************************************/ 38 #define TEGRA_IRAM_BASE 0x40000000 39 40 /******************************************************************************* 41 * GIC memory map 42 ******************************************************************************/ 43 #define TEGRA_GICD_BASE U(0x50041000) 44 #define TEGRA_GICC_BASE U(0x50042000) 45 46 /******************************************************************************* 47 * Secure IRQ definitions 48 ******************************************************************************/ 49 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 50 51 /******************************************************************************* 52 * Tegra Memory Select Switch Controller constants 53 ******************************************************************************/ 54 #define TEGRA_MSELECT_BASE U(0x50060000) 55 56 #define MSELECT_CONFIG U(0x0) 57 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 58 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 59 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 60 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 61 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 62 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 63 UNSUPPORTED_TX_ERR_MASTER1_BIT) 64 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 65 ENABLE_WRAP_INCR_MASTER1_BIT | \ 66 ENABLE_WRAP_INCR_MASTER0_BIT) 67 68 /******************************************************************************* 69 * Tegra Resource Semaphore constants 70 ******************************************************************************/ 71 #define TEGRA_RES_SEMA_BASE 0x60001000UL 72 #define STA_OFFSET 0UL 73 #define SET_OFFSET 4UL 74 #define CLR_OFFSET 8UL 75 76 /******************************************************************************* 77 * Tegra Primary Interrupt Controller constants 78 ******************************************************************************/ 79 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 80 #define CPU_IEP_FIR_SET 0x18UL 81 82 /******************************************************************************* 83 * Tegra micro-seconds timer constants 84 ******************************************************************************/ 85 #define TEGRA_TMRUS_BASE U(0x60005010) 86 #define TEGRA_TMRUS_SIZE U(0x1000) 87 88 /******************************************************************************* 89 * Tegra Clock and Reset Controller constants 90 ******************************************************************************/ 91 #define TEGRA_CAR_RESET_BASE U(0x60006000) 92 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 93 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 94 #define GPU_RESET_BIT (U(1) << 24) 95 #define GPU_SET_BIT (U(1) << 24) 96 #define TEGRA_RST_DEV_CLR_V U(0x434) 97 #define TEGRA_CLK_ENB_V U(0x440) 98 99 /* SE Clock Offsets */ 100 #define TEGRA_RST_DEVICES_V 0x358UL 101 #define SE_RESET_BIT (0x1UL << 31) 102 #define TEGRA_RST_DEVICES_W 0x35CUL 103 #define ENTROPY_CLK_ENB_BIT (0x1UL << 21) 104 #define TEGRA_CLK_OUT_ENB_V 0x360UL 105 #define SE_CLK_ENB_BIT (0x1UL << 31) 106 #define TEGRA_CLK_OUT_ENB_W 0x364UL 107 #define ENTROPY_RESET_BIT (0x1UL << 21) 108 109 /******************************************************************************* 110 * Tegra Flow Controller constants 111 ******************************************************************************/ 112 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 113 114 /******************************************************************************* 115 * Tegra AHB arbitration controller 116 ******************************************************************************/ 117 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 118 119 /******************************************************************************* 120 * Tegra Secure Boot Controller constants 121 ******************************************************************************/ 122 #define TEGRA_SB_BASE U(0x6000C200) 123 124 /******************************************************************************* 125 * Tegra Exception Vectors constants 126 ******************************************************************************/ 127 #define TEGRA_EVP_BASE U(0x6000F000) 128 129 /******************************************************************************* 130 * Tegra Miscellaneous register constants 131 ******************************************************************************/ 132 #define TEGRA_MISC_BASE U(0x70000000) 133 #define HARDWARE_REVISION_OFFSET U(0x804) 134 135 /******************************************************************************* 136 * Tegra UART controller base addresses 137 ******************************************************************************/ 138 #define TEGRA_UARTA_BASE U(0x70006000) 139 #define TEGRA_UARTB_BASE U(0x70006040) 140 #define TEGRA_UARTC_BASE U(0x70006200) 141 #define TEGRA_UARTD_BASE U(0x70006300) 142 #define TEGRA_UARTE_BASE U(0x70006400) 143 144 /******************************************************************************* 145 * Tegra Fuse Controller related constants 146 ******************************************************************************/ 147 #define TEGRA_FUSE_BASE 0x7000F800UL 148 #define FUSE_BOOT_SECURITY_INFO 0x268UL 149 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 150 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 151 #define ECID_VALID (0x1UL) 152 153 154 /******************************************************************************* 155 * Tegra Power Mgmt Controller constants 156 ******************************************************************************/ 157 #define TEGRA_PMC_BASE U(0x7000E400) 158 159 /******************************************************************************* 160 * Tegra Atomics constants 161 ******************************************************************************/ 162 #define TEGRA_ATOMICS_BASE 0x70016000UL 163 #define TRIGGER0_REG_OFFSET 0UL 164 #define TRIGGER_WIDTH_SHIFT 4UL 165 #define TRIGGER_ID_SHIFT 16UL 166 #define RESULT0_REG_OFFSET 0xC00UL 167 168 /******************************************************************************* 169 * Tegra Memory Controller constants 170 ******************************************************************************/ 171 #define TEGRA_MC_BASE U(0x70019000) 172 173 /* Memory Controller Interrupt Status */ 174 #define MC_INTSTATUS 0x00U 175 176 /* TZDRAM carveout configuration registers */ 177 #define MC_SECURITY_CFG0_0 U(0x70) 178 #define MC_SECURITY_CFG1_0 U(0x74) 179 #define MC_SECURITY_CFG3_0 U(0x9BC) 180 181 /* Video Memory carveout configuration registers */ 182 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 183 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 184 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 185 186 /* SMMU configuration registers*/ 187 #define MC_SMMU_PPCS_ASID_0 0x270U 188 #define PPCS_SMMU_ENABLE (0x1U << 31) 189 190 /******************************************************************************* 191 * Tegra SE constants 192 ******************************************************************************/ 193 #define TEGRA_SE1_BASE U(0x70012000) 194 #define TEGRA_SE2_BASE U(0x70412000) 195 #define TEGRA_PKA1_BASE U(0x70420000) 196 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 197 #define SE_TZRAM_SECURITY U(0x4) 198 199 /******************************************************************************* 200 * Tegra TZRAM constants 201 ******************************************************************************/ 202 #define TEGRA_TZRAM_BASE U(0x7C010000) 203 #define TEGRA_TZRAM_SIZE U(0x10000) 204 205 /******************************************************************************* 206 * Tegra TZRAM carveout constants 207 ******************************************************************************/ 208 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 209 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 210 211 #endif /* TEGRA_DEF_H */ 212