1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_SOC_POWERDN U(27) 18 19 /******************************************************************************* 20 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 21 * call as the `state-id` field in the 'power state' parameter. 22 ******************************************************************************/ 23 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 24 25 /******************************************************************************* 26 * Platform power states (used by PSCI framework) 27 * 28 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 29 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 30 ******************************************************************************/ 31 #define PLAT_MAX_RET_STATE U(1) 32 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 33 34 /******************************************************************************* 35 * Chip specific page table and MMU setup constants 36 ******************************************************************************/ 37 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 38 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 39 40 /******************************************************************************* 41 * iRAM memory constants 42 ******************************************************************************/ 43 #define TEGRA_IRAM_BASE U(0x40000000) 44 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */ 45 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */ 46 47 /******************************************************************************* 48 * GIC memory map 49 ******************************************************************************/ 50 #define TEGRA_GICD_BASE U(0x50041000) 51 #define TEGRA_GICC_BASE U(0x50042000) 52 53 /******************************************************************************* 54 * Secure IRQ definitions 55 ******************************************************************************/ 56 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 57 58 /******************************************************************************* 59 * Tegra Memory Select Switch Controller constants 60 ******************************************************************************/ 61 #define TEGRA_MSELECT_BASE U(0x50060000) 62 63 #define MSELECT_CONFIG U(0x0) 64 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 65 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 66 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 67 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 68 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 69 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 70 UNSUPPORTED_TX_ERR_MASTER1_BIT) 71 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 72 ENABLE_WRAP_INCR_MASTER1_BIT | \ 73 ENABLE_WRAP_INCR_MASTER0_BIT) 74 75 /******************************************************************************* 76 * Tegra Resource Semaphore constants 77 ******************************************************************************/ 78 #define TEGRA_RES_SEMA_BASE 0x60001000UL 79 #define STA_OFFSET 0UL 80 #define SET_OFFSET 4UL 81 #define CLR_OFFSET 8UL 82 83 /******************************************************************************* 84 * Tegra Primary Interrupt Controller constants 85 ******************************************************************************/ 86 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 87 #define CPU_IEP_FIR_SET 0x18UL 88 89 /******************************************************************************* 90 * Tegra micro-seconds timer constants 91 ******************************************************************************/ 92 #define TEGRA_TMRUS_BASE U(0x60005010) 93 #define TEGRA_TMRUS_SIZE U(0x1000) 94 95 /******************************************************************************* 96 * Tegra Clock and Reset Controller constants 97 ******************************************************************************/ 98 #define TEGRA_CAR_RESET_BASE U(0x60006000) 99 #define TEGRA_BOND_OUT_H U(0x74) 100 #define APB_DMA_LOCK_BIT (U(1) << 2) 101 #define AHB_DMA_LOCK_BIT (U(1) << 1) 102 #define TEGRA_BOND_OUT_U U(0x78) 103 #define IRAM_D_LOCK_BIT (U(1) << 23) 104 #define IRAM_C_LOCK_BIT (U(1) << 22) 105 #define IRAM_B_LOCK_BIT (U(1) << 21) 106 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 107 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 108 #define GPU_RESET_BIT (U(1) << 24) 109 #define GPU_SET_BIT (U(1) << 24) 110 #define TEGRA_RST_DEV_SET_Y U(0x2a8) 111 #define NVENC_RESET_BIT (U(1) << 27) 112 #define TSECB_RESET_BIT (U(1) << 14) 113 #define APE_RESET_BIT (U(1) << 6) 114 #define NVJPG_RESET_BIT (U(1) << 3) 115 #define NVDEC_RESET_BIT (U(1) << 2) 116 #define TEGRA_RST_DEV_SET_L U(0x300) 117 #define HOST1X_RESET_BIT (U(1) << 28) 118 #define ISP_RESET_BIT (U(1) << 23) 119 #define USBD_RESET_BIT (U(1) << 22) 120 #define VI_RESET_BIT (U(1) << 20) 121 #define SDMMC4_RESET_BIT (U(1) << 15) 122 #define SDMMC1_RESET_BIT (U(1) << 14) 123 #define SDMMC2_RESET_BIT (U(1) << 9) 124 #define TEGRA_RST_DEV_SET_H U(0x308) 125 #define USB2_RESET_BIT (U(1) << 26) 126 #define APBDMA_RESET_BIT (U(1) << 2) 127 #define AHBDMA_RESET_BIT (U(1) << 1) 128 #define TEGRA_RST_DEV_SET_U U(0x310) 129 #define XUSB_DEV_RESET_BIT (U(1) << 31) 130 #define XUSB_HOST_RESET_BIT (U(1) << 25) 131 #define TSEC_RESET_BIT (U(1) << 19) 132 #define PCIE_RESET_BIT (U(1) << 6) 133 #define SDMMC3_RESET_BIT (U(1) << 5) 134 #define TEGRA_RST_DEVICES_V U(0x358) 135 #define TEGRA_RST_DEVICES_W U(0x35C) 136 #define ENTROPY_CLK_ENB_BIT (U(1) << 21) 137 #define TEGRA_CLK_OUT_ENB_V U(0x360) 138 #define SE_CLK_ENB_BIT (U(1) << 31) 139 #define TEGRA_CLK_OUT_ENB_W U(0x364) 140 #define ENTROPY_RESET_BIT (U(1) << 21) 141 #define TEGRA_RST_DEV_SET_V U(0x430) 142 #define SE_RESET_BIT (U(1) << 31) 143 #define HDA_RESET_BIT (U(1) << 29) 144 #define SATA_RESET_BIT (U(1) << 28) 145 #define TEGRA_RST_DEV_CLR_V U(0x434) 146 #define TEGRA_CLK_ENB_V U(0x440) 147 148 /******************************************************************************* 149 * Tegra Flow Controller constants 150 ******************************************************************************/ 151 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 152 153 /******************************************************************************* 154 * Tegra AHB arbitration controller 155 ******************************************************************************/ 156 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 157 158 /******************************************************************************* 159 * Tegra Secure Boot Controller constants 160 ******************************************************************************/ 161 #define TEGRA_SB_BASE U(0x6000C200) 162 163 /******************************************************************************* 164 * Tegra Exception Vectors constants 165 ******************************************************************************/ 166 #define TEGRA_EVP_BASE U(0x6000F000) 167 168 /******************************************************************************* 169 * Tegra Miscellaneous register constants 170 ******************************************************************************/ 171 #define TEGRA_MISC_BASE U(0x70000000) 172 #define HARDWARE_REVISION_OFFSET U(0x804) 173 #define PINMUX_AUX_DVFS_PWM U(0x3184) 174 #define PINMUX_PWM_TRISTATE (U(1) << 4) 175 176 /******************************************************************************* 177 * Tegra UART controller base addresses 178 ******************************************************************************/ 179 #define TEGRA_UARTA_BASE U(0x70006000) 180 #define TEGRA_UARTB_BASE U(0x70006040) 181 #define TEGRA_UARTC_BASE U(0x70006200) 182 #define TEGRA_UARTD_BASE U(0x70006300) 183 #define TEGRA_UARTE_BASE U(0x70006400) 184 185 /******************************************************************************* 186 * Tegra Fuse Controller related constants 187 ******************************************************************************/ 188 #define TEGRA_FUSE_BASE 0x7000F800UL 189 #define FUSE_BOOT_SECURITY_INFO 0x268UL 190 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 191 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 192 #define ECID_VALID (0x1UL) 193 194 195 /******************************************************************************* 196 * Tegra Power Mgmt Controller constants 197 ******************************************************************************/ 198 #define TEGRA_PMC_BASE U(0x7000E400) 199 #define TEGRA_PMC_SIZE U(0xC00) /* 3k */ 200 201 /******************************************************************************* 202 * Tegra Atomics constants 203 ******************************************************************************/ 204 #define TEGRA_ATOMICS_BASE 0x70016000UL 205 #define TRIGGER0_REG_OFFSET 0UL 206 #define TRIGGER_WIDTH_SHIFT 4UL 207 #define TRIGGER_ID_SHIFT 16UL 208 #define RESULT0_REG_OFFSET 0xC00UL 209 210 /******************************************************************************* 211 * Tegra Memory Controller constants 212 ******************************************************************************/ 213 #define TEGRA_MC_BASE U(0x70019000) 214 215 /* Memory Controller Interrupt Status */ 216 #define MC_INTSTATUS 0x00U 217 218 /* TZDRAM carveout configuration registers */ 219 #define MC_SECURITY_CFG0_0 U(0x70) 220 #define MC_SECURITY_CFG1_0 U(0x74) 221 #define MC_SECURITY_CFG3_0 U(0x9BC) 222 223 /* Video Memory carveout configuration registers */ 224 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 225 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 226 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 227 228 /* SMMU configuration registers*/ 229 #define MC_SMMU_PPCS_ASID_0 0x270U 230 #define PPCS_SMMU_ENABLE (0x1U << 31) 231 232 /******************************************************************************* 233 * Tegra CLDVFS constants 234 ******************************************************************************/ 235 #define TEGRA_CL_DVFS_BASE U(0x70110000) 236 #define DVFS_DFLL_CTRL U(0x00) 237 #define ENABLE_OPEN_LOOP U(1) 238 #define ENABLE_CLOSED_LOOP U(2) 239 #define DVFS_DFLL_OUTPUT_CFG U(0x20) 240 #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30) 241 #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6) 242 243 /******************************************************************************* 244 * Tegra SE constants 245 ******************************************************************************/ 246 #define TEGRA_SE1_BASE U(0x70012000) 247 #define TEGRA_SE2_BASE U(0x70412000) 248 #define TEGRA_PKA1_BASE U(0x70420000) 249 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 250 #define SE_TZRAM_SECURITY U(0x4) 251 252 /******************************************************************************* 253 * Tegra TZRAM constants 254 ******************************************************************************/ 255 #define TEGRA_TZRAM_BASE U(0x7C010000) 256 #define TEGRA_TZRAM_SIZE U(0x10000) 257 258 /******************************************************************************* 259 * Tegra TZRAM carveout constants 260 ******************************************************************************/ 261 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 262 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 263 264 #endif /* TEGRA_DEF_H */ 265