1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <pmc.h> 19 #include <platform_def.h> 20 #include <security_engine.h> 21 #include <tegra_def.h> 22 #include <tegra_private.h> 23 #include <tegra_platform.h> 24 25 /* 26 * Register used to clear CPU reset signals. Each CPU has two reset 27 * signals: CPU reset (3:0) and Core reset (19:16). 28 */ 29 #define CPU_CMPLX_RESET_CLR 0x454 30 #define CPU_CORE_RESET_MASK 0x10001 31 32 /* Clock and Reset controller registers for system clock's settings */ 33 #define SCLK_RATE 0x30 34 #define SCLK_BURST_POLICY 0x28 35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 36 37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 38 static bool tegra_bpmp_available = true; 39 40 int32_t tegra_soc_validate_power_state(unsigned int power_state, 41 psci_power_state_t *req_state) 42 { 43 int state_id = psci_get_pstate_id(power_state); 44 45 /* Sanity check the requested state id */ 46 switch (state_id) { 47 case PSTATE_ID_CORE_POWERDN: 48 /* 49 * Core powerdown request only for afflvl 0 50 */ 51 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 52 53 break; 54 55 case PSTATE_ID_CLUSTER_IDLE: 56 case PSTATE_ID_CLUSTER_POWERDN: 57 58 /* 59 * Cluster idle request for afflvl 0 60 */ 61 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 62 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 63 64 break; 65 66 case PSTATE_ID_SOC_POWERDN: 67 /* 68 * System powerdown request only for afflvl 2 69 */ 70 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 71 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 72 73 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 74 PLAT_SYS_SUSPEND_STATE_ID; 75 76 break; 77 78 default: 79 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 80 return PSCI_E_INVALID_PARAMS; 81 } 82 83 return PSCI_E_SUCCESS; 84 } 85 86 /******************************************************************************* 87 * Platform handler to calculate the proper target power level at the 88 * specified affinity level. 89 ******************************************************************************/ 90 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 91 const plat_local_state_t *states, 92 unsigned int ncpu) 93 { 94 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 95 int cpu = plat_my_core_pos(); 96 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 97 uint32_t bpmp_reply, data[3], val; 98 int ret; 99 100 /* get the power state at this level */ 101 if (lvl == MPIDR_AFFLVL1) 102 target = *(states + core_pos); 103 if (lvl == MPIDR_AFFLVL2) 104 target = *(states + cpu); 105 106 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 107 108 /* initialize the bpmp interface */ 109 ret = tegra_bpmp_init(); 110 if (ret != 0U) { 111 112 /* Cluster idle not allowed */ 113 target = PSCI_LOCAL_STATE_RUN; 114 115 /******************************************* 116 * BPMP is not present, so handle CC6 entry 117 * from the CPU 118 ******************************************/ 119 120 /* check if cluster idle state has been enabled */ 121 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); 122 if (val == ENABLE_CLOSED_LOOP) { 123 /* 124 * flag to indicate that BPMP firmware is not 125 * available and the CPU has to handle entry/exit 126 * for all power states 127 */ 128 tegra_bpmp_available = false; 129 130 /* 131 * Acquire the cluster idle lock to stop 132 * other CPUs from powering up. 133 */ 134 tegra_fc_ccplex_pgexit_lock(); 135 136 /* Cluster idle only from the last standing CPU */ 137 if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { 138 /* Cluster idle allowed */ 139 target = PSTATE_ID_CLUSTER_IDLE; 140 } else { 141 /* release cluster idle lock */ 142 tegra_fc_ccplex_pgexit_unlock(); 143 } 144 } 145 } else { 146 147 /* Cluster power-down */ 148 data[0] = (uint32_t)cpu; 149 data[1] = TEGRA_PM_CC6; 150 data[2] = TEGRA_PM_SC1; 151 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 152 (void *)&data, (int)sizeof(data), 153 (void *)&bpmp_reply, 154 (int)sizeof(bpmp_reply)); 155 156 /* check if cluster power down is allowed */ 157 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 158 159 /* Cluster power down not allowed */ 160 target = PSCI_LOCAL_STATE_RUN; 161 } 162 } 163 164 } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) { 165 166 /* initialize the bpmp interface */ 167 ret = tegra_bpmp_init(); 168 if (ret != 0U) { 169 170 /* Cluster power down not allowed */ 171 target = PSCI_LOCAL_STATE_RUN; 172 } else { 173 174 /* Cluster power-down */ 175 data[0] = (uint32_t)cpu; 176 data[1] = TEGRA_PM_CC7; 177 data[2] = TEGRA_PM_SC1; 178 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 179 (void *)&data, (int)sizeof(data), 180 (void *)&bpmp_reply, 181 (int)sizeof(bpmp_reply)); 182 183 /* check if cluster power down is allowed */ 184 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 185 186 /* Cluster power down not allowed */ 187 target = PSCI_LOCAL_STATE_RUN; 188 } 189 } 190 191 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 192 (target == PSTATE_ID_SOC_POWERDN)) { 193 194 /* System Suspend */ 195 target = PSTATE_ID_SOC_POWERDN; 196 197 } else { 198 ; /* do nothing */ 199 } 200 201 return target; 202 } 203 204 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 205 { 206 u_register_t mpidr = read_mpidr(); 207 const plat_local_state_t *pwr_domain_state = 208 target_state->pwr_domain_state; 209 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 210 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 211 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 212 uint32_t cfg; 213 int ret = PSCI_E_SUCCESS; 214 uint32_t val; 215 216 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 217 218 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 219 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 220 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 221 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 222 223 if (tegra_chipid_is_t210_b01()) { 224 225 /* Suspend se/se2 and pka1 */ 226 if (tegra_se_suspend() != 0) { 227 ret = PSCI_E_INTERN_FAIL; 228 } 229 } 230 231 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 232 233 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 234 235 if (!tegra_bpmp_available) { 236 237 /* PWM tristate */ 238 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 239 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 240 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 241 val |= PINMUX_PWM_TRISTATE; 242 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 243 } 244 } 245 246 /* Prepare for cluster idle */ 247 tegra_fc_cluster_idle(mpidr); 248 249 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 250 251 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 252 253 /* Prepare for cluster powerdn */ 254 tegra_fc_cluster_powerdn(mpidr); 255 256 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 257 258 /* Prepare for cpu powerdn */ 259 tegra_fc_cpu_powerdn(mpidr); 260 261 } else { 262 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 263 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 264 ret = PSCI_E_NOT_SUPPORTED; 265 } 266 267 return ret; 268 } 269 270 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 271 { 272 u_register_t mpidr = read_mpidr(); 273 const plat_local_state_t *pwr_domain_state = 274 target_state->pwr_domain_state; 275 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 276 277 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 278 279 if (tegra_chipid_is_t210_b01()) { 280 /* Save tzram contents */ 281 tegra_se_save_tzram(); 282 } 283 284 /* enter system suspend */ 285 tegra_fc_soc_powerdn(mpidr); 286 } 287 288 return PSCI_E_SUCCESS; 289 } 290 291 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 292 { 293 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 294 uint32_t cfg; 295 uint32_t val; 296 297 /* platform parameter passed by the previous bootloader */ 298 if (plat_params->l2_ecc_parity_prot_dis != 1) { 299 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 300 val = read_l2ctlr_el1(); 301 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 302 write_l2ctlr_el1(val); 303 } 304 305 /* 306 * Check if we are exiting from SOC_POWERDN. 307 */ 308 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 309 PLAT_SYS_SUSPEND_STATE_ID) { 310 311 /* 312 * Security engine resume 313 */ 314 if (tegra_chipid_is_t210_b01()) { 315 tegra_se_resume(); 316 } 317 318 /* 319 * Lock scratch registers which hold the CPU vectors 320 */ 321 tegra_pmc_lock_cpu_vectors(); 322 323 /* 324 * Enable WRAP to INCR burst type conversions for 325 * incoming requests on the AXI slave ports. 326 */ 327 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 328 val &= ~ENABLE_UNSUP_TX_ERRORS; 329 val |= ENABLE_WRAP_TO_INCR_BURSTS; 330 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 331 332 /* 333 * Restore Boot and Power Management Processor (BPMP) reset 334 * address and reset it. 335 */ 336 if (tegra_bpmp_available) 337 tegra_fc_reset_bpmp(); 338 } 339 340 /* 341 * Check if we are exiting cluster idle state 342 */ 343 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == 344 PSTATE_ID_CLUSTER_IDLE) { 345 346 if (!tegra_bpmp_available) { 347 348 /* PWM un-tristate */ 349 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); 350 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { 351 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); 352 val &= ~PINMUX_PWM_TRISTATE; 353 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); 354 } 355 356 /* release cluster idle lock */ 357 tegra_fc_ccplex_pgexit_unlock(); 358 } 359 } 360 361 /* 362 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 363 * used for power management and boot purposes. Inform the BPMP that 364 * we have completed the cluster power up. 365 */ 366 tegra_fc_lock_active_cluster(); 367 368 return PSCI_E_SUCCESS; 369 } 370 371 int tegra_soc_pwr_domain_on(u_register_t mpidr) 372 { 373 int cpu = mpidr & MPIDR_CPU_MASK; 374 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 375 376 /* Deassert CPU reset signals */ 377 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 378 379 /* Turn on CPU using flow controller or PMC */ 380 if (cpu_powergate_mask[cpu] == 0) { 381 tegra_pmc_cpu_on(cpu); 382 cpu_powergate_mask[cpu] = 1; 383 } else { 384 tegra_fc_cpu_on(cpu); 385 } 386 387 return PSCI_E_SUCCESS; 388 } 389 390 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 391 { 392 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 393 return PSCI_E_SUCCESS; 394 } 395 396 int tegra_soc_prepare_system_reset(void) 397 { 398 /* 399 * Set System Clock (SCLK) to POR default so that the clock source 400 * for the PMC APB clock would not be changed due to system reset. 401 */ 402 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 403 SCLK_BURST_POLICY_DEFAULT); 404 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 405 406 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 407 mdelay(1); 408 409 return PSCI_E_SUCCESS; 410 } 411