1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MEMCTRL_V2_H 8 #define MEMCTRL_V2_H 9 10 #include <tegra_def.h> 11 12 #ifndef __ASSEMBLY__ 13 14 #include <stdint.h> 15 16 /******************************************************************************* 17 * StreamID to indicate no SMMU translations (requests to be steered on the 18 * SMMU bypass path) 19 ******************************************************************************/ 20 #define MC_STREAM_ID_MAX 0x7FU 21 22 /******************************************************************************* 23 * Stream ID Override Config registers 24 ******************************************************************************/ 25 #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000U 26 #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070U 27 #define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8U 28 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0U 29 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0U 30 #define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8U 31 #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U 32 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U 33 #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188U 34 #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8U 35 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8U 36 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8U 37 #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U 38 #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U 39 #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U 40 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U 41 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U 42 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U 43 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U 44 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0U 45 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8U 46 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0U 47 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8U 48 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U 49 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308U 50 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U 51 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U 52 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U 53 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328U 54 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U 55 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U 56 #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U 57 #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U 58 #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U 59 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0U 60 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8U 61 #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0U 62 #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8U 63 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0U 64 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8U 65 #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U 66 #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U 67 #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U 68 #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U 69 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U 70 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U 71 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440U 72 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448U 73 #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U 74 #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U 75 #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U 76 #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U 77 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U 78 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U 79 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U 80 #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U 81 #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0U 82 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8U 83 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0U 84 #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8U 85 #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0U 86 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8U 87 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0U 88 #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8U 89 #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0U 90 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8U 91 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0U 92 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8U 93 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U 94 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U 95 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U 96 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U 97 98 /******************************************************************************* 99 * Macro to calculate Security cfg register addr from StreamID Override register 100 ******************************************************************************/ 101 #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t)) 102 103 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4) 104 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4) 105 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4) 106 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4) 107 108 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8) 109 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8) 110 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8) 111 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8) 112 113 #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12) 114 #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12) 115 116 /******************************************************************************* 117 * Memory Controller transaction override config registers 118 ******************************************************************************/ 119 #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U 120 #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U 121 #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U 122 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U 123 #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U 124 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U 125 #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U 126 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328U 127 #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U 128 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U 129 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0U 130 #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U 131 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U 132 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U 133 #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U 134 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U 135 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U 136 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U 137 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U 138 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U 139 #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U 140 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308U 141 #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U 142 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U 143 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U 144 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U 145 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8U 146 #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U 147 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U 148 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U 149 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440U 150 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U 151 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448U 152 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U 153 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U 154 #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U 155 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U 156 #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U 157 #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U 158 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U 159 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U 160 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U 161 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U 162 #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U 163 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U 164 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U 165 #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U 166 #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U 167 #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U 168 #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U 169 #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U 170 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U 171 #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U 172 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U 173 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U 174 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U 175 #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U 176 #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U 177 #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U 178 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U 179 #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070U 180 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U 181 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U 182 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U 183 #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U 184 #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U 185 #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U 186 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U 187 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U 188 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U 189 #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188U 190 #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U 191 192 /******************************************************************************* 193 * Structure to hold the transaction override settings to use to override 194 * client inputs 195 ******************************************************************************/ 196 typedef struct mc_txn_override_cfg { 197 uint32_t offset; 198 uint8_t cgid_tag; 199 } mc_txn_override_cfg_t; 200 201 #define mc_make_txn_override_cfg(off, val) \ 202 { \ 203 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 204 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 205 } 206 207 /******************************************************************************* 208 * Structure to hold the Stream ID to use to override client inputs 209 ******************************************************************************/ 210 typedef struct mc_streamid_override_cfg { 211 uint32_t offset; 212 uint8_t stream_id; 213 } mc_streamid_override_cfg_t; 214 215 /******************************************************************************* 216 * Structure to hold the Stream ID Security Configuration settings 217 ******************************************************************************/ 218 typedef struct mc_streamid_security_cfg { 219 char *name; 220 uint32_t offset; 221 int override_enable; 222 int override_client_inputs; 223 int override_client_ns_flag; 224 } mc_streamid_security_cfg_t; 225 226 #define OVERRIDE_DISABLE 1U 227 #define OVERRIDE_ENABLE 0U 228 #define CLIENT_FLAG_SECURE 0U 229 #define CLIENT_FLAG_NON_SECURE 1U 230 #define CLIENT_INPUTS_OVERRIDE 1U 231 #define CLIENT_INPUTS_NO_OVERRIDE 0U 232 233 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 234 { \ 235 .name = # off, \ 236 .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ 237 MC_STREAMID_OVERRIDE_CFG_ ## off), \ 238 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 239 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 240 .override_enable = OVERRIDE_ ## access \ 241 } 242 243 /******************************************************************************* 244 * Structure to hold Memory Controller's Configuration settings 245 ******************************************************************************/ 246 typedef struct tegra_mc_settings { 247 const uint32_t *streamid_override_cfg; 248 uint32_t num_streamid_override_cfgs; 249 const mc_streamid_security_cfg_t *streamid_security_cfg; 250 uint32_t num_streamid_security_cfgs; 251 const mc_txn_override_cfg_t *txn_override_cfg; 252 uint32_t num_txn_override_cfgs; 253 } tegra_mc_settings_t; 254 255 #endif /* __ASSEMBLY__ */ 256 257 /******************************************************************************* 258 * Memory Controller SMMU Bypass config register 259 ******************************************************************************/ 260 #define MC_SMMU_BYPASS_CONFIG 0x1820U 261 #define MC_SMMU_BYPASS_CTRL_MASK 0x3U 262 #define MC_SMMU_BYPASS_CTRL_SHIFT 0U 263 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT) 264 #define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT) 265 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT) 266 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT) 267 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31) 268 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 269 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 270 271 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0) 272 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4) 273 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12) 274 275 /******************************************************************************* 276 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 277 * MC_TXN_OVERRIDE_CONFIG_{module} registers 278 ******************************************************************************/ 279 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U 280 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U 281 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U 282 #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U 283 #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3U 284 285 /******************************************************************************* 286 * Memory Controller Reset Control registers 287 ******************************************************************************/ 288 #define MC_CLIENT_HOTRESET_CTRL0 0x200U 289 #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U 290 #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0) 291 #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6) 292 #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7) 293 #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8) 294 #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9) 295 #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11) 296 #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15) 297 #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17) 298 #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18) 299 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19) 300 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20) 301 #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22) 302 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29) 303 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30) 304 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31) 305 #define MC_CLIENT_HOTRESET_STATUS0 0x204U 306 #define MC_CLIENT_HOTRESET_CTRL1 0x970U 307 #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U 308 #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0) 309 #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2) 310 #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5) 311 #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6) 312 #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7) 313 #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8) 314 #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12) 315 #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13) 316 #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 18) 317 #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 19) 318 #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 20) 319 #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 21) 320 #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 22) 321 #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 23) 322 #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24) 323 #define MC_CLIENT_HOTRESET_STATUS1 0x974U 324 325 /******************************************************************************* 326 * Memory Controller's PCFIFO client configuration registers 327 ******************************************************************************/ 328 #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4UL 329 #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000UL 330 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0UL << 17) 331 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1UL << 17) 332 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0UL << 21) 333 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1UL << 21) 334 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0UL << 29) 335 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1UL << 29) 336 337 #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8UL 338 #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000UL 339 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0UL << 11) 340 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1UL << 11) 341 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0UL << 13) 342 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1UL << 13) 343 344 #define MC_PCFIFO_CLIENT_CONFIG3 0xddcUL 345 #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0UL 346 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0UL << 7) 347 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1UL << 7) 348 349 #define MC_PCFIFO_CLIENT_CONFIG4 0xde0UL 350 #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0UL 351 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0UL << 1) 352 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1UL << 1) 353 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0UL << 5) 354 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1UL << 5) 355 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0UL << 13) 356 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1UL << 13) 357 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0UL << 15) 358 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1UL << 15) 359 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1UL << 15) 360 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0UL << 17) 361 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1UL << 17) 362 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0UL << 22) 363 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1UL << 22) 364 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0UL << 26) 365 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1UL << 26) 366 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0UL << 30) 367 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1UL << 30) 368 369 #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4UL 370 #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0UL 371 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0UL << 0) 372 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1UL << 0) 373 374 #ifndef __ASSEMBLY__ 375 376 #include <lib/mmio.h> 377 378 static inline uint32_t tegra_mc_read_32(uint32_t off) 379 { 380 return mmio_read_32(TEGRA_MC_BASE + off); 381 } 382 383 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 384 { 385 mmio_write_32(TEGRA_MC_BASE + off, val); 386 } 387 388 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 389 { 390 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 391 } 392 393 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 394 { 395 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 396 } 397 398 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 399 ((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 400 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 401 402 #define mc_set_pcfifo_ordered_boot_so_mss(id, client) \ 403 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED 404 405 #define mc_set_tsa_passthrough(client) \ 406 { \ 407 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 408 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 409 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 410 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 411 } 412 413 #define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \ 414 { \ 415 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 416 MC_TXN_OVERRIDE_##normal_axi_id | \ 417 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \ 418 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \ 419 MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ 420 } 421 422 /******************************************************************************* 423 * Handler to read memory configuration settings 424 * 425 * Implemented by SoCs under tegra/soc/txxx 426 ******************************************************************************/ 427 tegra_mc_settings_t *tegra_get_mc_settings(void); 428 429 #endif /* __ASSMEBLY__ */ 430 431 #endif /* MEMCTRL_V2_H */ 432