1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cortex_a57.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/console.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <drivers/arm/gic_common.h> 16 #include <drivers/arm/gicv2.h> 17 #include <bl31/interrupt_mgmt.h> 18 19 #include <bpmp.h> 20 #include <flowctrl.h> 21 #include <platform.h> 22 #include <security_engine.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 #include <tegra_private.h> 26 27 /* sets of MMIO ranges setup */ 28 #define MMIO_RANGE_0_ADDR 0x50000000 29 #define MMIO_RANGE_1_ADDR 0x60000000 30 #define MMIO_RANGE_2_ADDR 0x70000000 31 #define MMIO_RANGE_SIZE 0x200000 32 33 /* 34 * Table of regions to map using the MMU. 35 */ 36 static const mmap_region_t tegra_mmap[] = { 37 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 38 MT_DEVICE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 {0} 46 }; 47 48 /******************************************************************************* 49 * Set up the pagetables as per the platform memory map & initialize the MMU 50 ******************************************************************************/ 51 const mmap_region_t *plat_get_mmio_map(void) 52 { 53 /* Add the map region for security engine SE2 */ 54 if (tegra_chipid_is_t210_b01()) { 55 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 56 (uint64_t)TEGRA_SE2_BASE, 57 (uint64_t)TEGRA_SE2_RANGE_SIZE, 58 MT_DEVICE | MT_RW | MT_SECURE); 59 } 60 61 /* MMIO space */ 62 return tegra_mmap; 63 } 64 65 /******************************************************************************* 66 * The Tegra power domain tree has a single system level power domain i.e. a 67 * single root node. The first entry in the power domain descriptor specifies 68 * the number of power domains at the highest power level. 69 ******************************************************************************* 70 */ 71 const unsigned char tegra_power_domain_tree_desc[] = { 72 /* No of root nodes */ 73 1, 74 /* No of clusters */ 75 PLATFORM_CLUSTER_COUNT, 76 /* No of CPU cores - cluster0 */ 77 PLATFORM_MAX_CPUS_PER_CLUSTER, 78 /* No of CPU cores - cluster1 */ 79 PLATFORM_MAX_CPUS_PER_CLUSTER 80 }; 81 82 /******************************************************************************* 83 * This function returns the Tegra default topology tree information. 84 ******************************************************************************/ 85 const unsigned char *plat_get_power_domain_tree_desc(void) 86 { 87 return tegra_power_domain_tree_desc; 88 } 89 90 /******************************************************************************* 91 * Handler to get the System Counter Frequency 92 ******************************************************************************/ 93 unsigned int plat_get_syscnt_freq2(void) 94 { 95 return 19200000; 96 } 97 98 /******************************************************************************* 99 * Maximum supported UART controllers 100 ******************************************************************************/ 101 #define TEGRA210_MAX_UART_PORTS 5 102 103 /******************************************************************************* 104 * This variable holds the UART port base addresses 105 ******************************************************************************/ 106 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 107 0, /* undefined - treated as an error case */ 108 TEGRA_UARTA_BASE, 109 TEGRA_UARTB_BASE, 110 TEGRA_UARTC_BASE, 111 TEGRA_UARTD_BASE, 112 TEGRA_UARTE_BASE, 113 }; 114 115 /******************************************************************************* 116 * Retrieve the UART controller base to be used as the console 117 ******************************************************************************/ 118 uint32_t plat_get_console_from_id(int id) 119 { 120 if (id > TEGRA210_MAX_UART_PORTS) 121 return 0; 122 123 return tegra210_uart_addresses[id]; 124 } 125 126 /******************************************************************************* 127 * Handler for early platform setup 128 ******************************************************************************/ 129 void plat_early_platform_setup(void) 130 { 131 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 132 uint64_t val; 133 134 /* platform parameter passed by the previous bootloader */ 135 if (plat_params->l2_ecc_parity_prot_dis != 1) { 136 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 137 val = read_l2ctlr_el1(); 138 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 139 write_l2ctlr_el1(val); 140 } 141 142 /* Initialize security engine driver */ 143 if (tegra_chipid_is_t210_b01()) { 144 tegra_se_init(); 145 } 146 } 147 148 /* Secure IRQs for Tegra186 */ 149 static const interrupt_prop_t tegra210_interrupt_props[] = { 150 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY, 151 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 152 }; 153 154 void plat_late_platform_setup(void) 155 { 156 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 157 uint64_t tzdram_start, tzdram_end, sc7entry_end; 158 int ret; 159 160 /* memmap TZDRAM area containing the SC7 Entry Firmware */ 161 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { 162 163 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_SIZE); 164 165 /* 166 * Verify that the SC7 entry firmware resides inside the TZDRAM 167 * aperture, _after_ the BL31 code. 168 */ 169 tzdram_start = plat_params->tzdram_base; 170 tzdram_end = plat_params->tzdram_base + plat_params->tzdram_size; 171 sc7entry_end = plat_params->sc7entry_fw_base + 172 plat_params->sc7entry_fw_size; 173 if ((plat_params->sc7entry_fw_base < (tzdram_start + BL31_SIZE)) || 174 (sc7entry_end > tzdram_end)) { 175 panic(); 176 } 177 178 /* power off BPMP processor until SC7 entry */ 179 tegra_fc_bpmp_off(); 180 181 /* memmap SC7 entry firmware code */ 182 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base, 183 plat_params->sc7entry_fw_base, 184 plat_params->sc7entry_fw_size, 185 MT_NS | MT_RO | MT_EXECUTE_NEVER); 186 assert(ret == 0); 187 } 188 } 189 190 /******************************************************************************* 191 * Initialize the GIC and SGIs 192 ******************************************************************************/ 193 void plat_gic_setup(void) 194 { 195 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props)); 196 197 /* Enable handling for FIQs */ 198 tegra_fiq_handler_setup(); 199 200 /* 201 * Enable routing watchdog FIQs from the flow controller to 202 * the GICD. 203 */ 204 tegra_fc_enable_fiq_to_ccplex_routing(); 205 } 206