xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/pmc.h (revision 3ca3c27cad16342e5f2b76511aa2e1d9cdb151a6)
1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PMC_H
8 #define PMC_H
9 
10 #include <lib/mmio.h>
11 #include <lib/utils_def.h>
12 #include <stdbool.h>
13 
14 #include <tegra_def.h>
15 
16 #define PMC_CONFIG				U(0x0)
17 #define PMC_PWRGATE_STATUS			U(0x38)
18 #define PMC_PWRGATE_TOGGLE			U(0x30)
19 #define  PMC_TOGGLE_START			U(0x100)
20 #define PMC_SCRATCH39				U(0x138)
21 #define PMC_SECURE_DISABLE2			U(0x2c4)
22 #define  PMC_SECURE_DISABLE2_WRITE22_ON		(U(1) << 28)
23 #define PMC_SECURE_SCRATCH22			U(0x338)
24 #define PMC_SECURE_DISABLE3			U(0x2d8)
25 #define  PMC_SECURE_DISABLE3_WRITE34_ON		(U(1) << 20)
26 #define  PMC_SECURE_DISABLE3_WRITE35_ON		(U(1) << 22)
27 #define PMC_SECURE_SCRATCH34			U(0x368)
28 #define PMC_SECURE_SCRATCH35			U(0x36c)
29 #define PMC_SCRATCH201				U(0x844)
30 
31 static inline uint32_t tegra_pmc_read_32(uint32_t off)
32 {
33 	return mmio_read_32(TEGRA_PMC_BASE + off);
34 }
35 
36 static inline void tegra_pmc_write_32(uint32_t off, uint32_t val)
37 {
38 	mmio_write_32(TEGRA_PMC_BASE + off, val);
39 }
40 
41 void tegra_pmc_cpu_on(int32_t cpu);
42 void tegra_pmc_cpu_setup(uint64_t reset_addr);
43 bool tegra_pmc_is_last_on_cpu(void);
44 void tegra_pmc_lock_cpu_vectors(void);
45 __dead2 void tegra_pmc_system_reset(void);
46 
47 #endif /* PMC_H */
48