1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_CLUSTER_POWERDN U(17) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * Chip specific page table and MMU setup constants 37 ******************************************************************************/ 38 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 39 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 40 41 /******************************************************************************* 42 * iRAM memory constants 43 ******************************************************************************/ 44 #define TEGRA_IRAM_BASE 0x40000000 45 46 /******************************************************************************* 47 * GIC memory map 48 ******************************************************************************/ 49 #define TEGRA_GICD_BASE U(0x50041000) 50 #define TEGRA_GICC_BASE U(0x50042000) 51 52 /******************************************************************************* 53 * Secure IRQ definitions 54 ******************************************************************************/ 55 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 56 57 /******************************************************************************* 58 * Tegra Memory Select Switch Controller constants 59 ******************************************************************************/ 60 #define TEGRA_MSELECT_BASE U(0x50060000) 61 62 #define MSELECT_CONFIG U(0x0) 63 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 64 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 65 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 66 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 67 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 68 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 69 UNSUPPORTED_TX_ERR_MASTER1_BIT) 70 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 71 ENABLE_WRAP_INCR_MASTER1_BIT | \ 72 ENABLE_WRAP_INCR_MASTER0_BIT) 73 74 /******************************************************************************* 75 * Tegra Resource Semaphore constants 76 ******************************************************************************/ 77 #define TEGRA_RES_SEMA_BASE 0x60001000UL 78 #define STA_OFFSET 0UL 79 #define SET_OFFSET 4UL 80 #define CLR_OFFSET 8UL 81 82 /******************************************************************************* 83 * Tegra Primary Interrupt Controller constants 84 ******************************************************************************/ 85 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 86 #define CPU_IEP_FIR_SET 0x18UL 87 88 /******************************************************************************* 89 * Tegra micro-seconds timer constants 90 ******************************************************************************/ 91 #define TEGRA_TMRUS_BASE U(0x60005010) 92 #define TEGRA_TMRUS_SIZE U(0x1000) 93 94 /******************************************************************************* 95 * Tegra Clock and Reset Controller constants 96 ******************************************************************************/ 97 #define TEGRA_CAR_RESET_BASE U(0x60006000) 98 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 99 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 100 #define GPU_RESET_BIT (U(1) << 24) 101 #define GPU_SET_BIT (U(1) << 24) 102 #define TEGRA_RST_DEV_CLR_V U(0x434) 103 #define TEGRA_CLK_ENB_V U(0x440) 104 105 /* SE Clock Offsets */ 106 #define TEGRA_RST_DEVICES_V 0x358UL 107 #define SE_RESET_BIT (0x1UL << 31) 108 #define TEGRA_RST_DEVICES_W 0x35CUL 109 #define ENTROPY_CLK_ENB_BIT (0x1UL << 21) 110 #define TEGRA_CLK_OUT_ENB_V 0x360UL 111 #define SE_CLK_ENB_BIT (0x1UL << 31) 112 #define TEGRA_CLK_OUT_ENB_W 0x364UL 113 #define ENTROPY_RESET_BIT (0x1UL << 21) 114 115 /******************************************************************************* 116 * Tegra Flow Controller constants 117 ******************************************************************************/ 118 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 119 120 /******************************************************************************* 121 * Tegra AHB arbitration controller 122 ******************************************************************************/ 123 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 124 125 /******************************************************************************* 126 * Tegra Secure Boot Controller constants 127 ******************************************************************************/ 128 #define TEGRA_SB_BASE U(0x6000C200) 129 130 /******************************************************************************* 131 * Tegra Exception Vectors constants 132 ******************************************************************************/ 133 #define TEGRA_EVP_BASE U(0x6000F000) 134 135 /******************************************************************************* 136 * Tegra Miscellaneous register constants 137 ******************************************************************************/ 138 #define TEGRA_MISC_BASE U(0x70000000) 139 #define HARDWARE_REVISION_OFFSET U(0x804) 140 141 /******************************************************************************* 142 * Tegra UART controller base addresses 143 ******************************************************************************/ 144 #define TEGRA_UARTA_BASE U(0x70006000) 145 #define TEGRA_UARTB_BASE U(0x70006040) 146 #define TEGRA_UARTC_BASE U(0x70006200) 147 #define TEGRA_UARTD_BASE U(0x70006300) 148 #define TEGRA_UARTE_BASE U(0x70006400) 149 150 /******************************************************************************* 151 * Tegra Fuse Controller related constants 152 ******************************************************************************/ 153 #define TEGRA_FUSE_BASE 0x7000F800UL 154 #define FUSE_BOOT_SECURITY_INFO 0x268UL 155 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 156 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 157 #define ECID_VALID (0x1UL) 158 159 160 /******************************************************************************* 161 * Tegra Power Mgmt Controller constants 162 ******************************************************************************/ 163 #define TEGRA_PMC_BASE U(0x7000E400) 164 165 /******************************************************************************* 166 * Tegra Atomics constants 167 ******************************************************************************/ 168 #define TEGRA_ATOMICS_BASE 0x70016000UL 169 #define TRIGGER0_REG_OFFSET 0UL 170 #define TRIGGER_WIDTH_SHIFT 4UL 171 #define TRIGGER_ID_SHIFT 16UL 172 #define RESULT0_REG_OFFSET 0xC00UL 173 174 /******************************************************************************* 175 * Tegra Memory Controller constants 176 ******************************************************************************/ 177 #define TEGRA_MC_BASE U(0x70019000) 178 179 /* Memory Controller Interrupt Status */ 180 #define MC_INTSTATUS 0x00U 181 182 /* TZDRAM carveout configuration registers */ 183 #define MC_SECURITY_CFG0_0 U(0x70) 184 #define MC_SECURITY_CFG1_0 U(0x74) 185 #define MC_SECURITY_CFG3_0 U(0x9BC) 186 187 /* Video Memory carveout configuration registers */ 188 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 189 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 190 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 191 192 /* SMMU configuration registers*/ 193 #define MC_SMMU_PPCS_ASID_0 0x270U 194 #define PPCS_SMMU_ENABLE (0x1U << 31) 195 196 /******************************************************************************* 197 * Tegra SE constants 198 ******************************************************************************/ 199 #define TEGRA_SE1_BASE U(0x70012000) 200 #define TEGRA_SE2_BASE U(0x70412000) 201 #define TEGRA_PKA1_BASE U(0x70420000) 202 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 203 #define SE_TZRAM_SECURITY U(0x4) 204 205 /******************************************************************************* 206 * Tegra TZRAM constants 207 ******************************************************************************/ 208 #define TEGRA_TZRAM_BASE U(0x7C010000) 209 #define TEGRA_TZRAM_SIZE U(0x10000) 210 211 /******************************************************************************* 212 * Tegra TZRAM carveout constants 213 ******************************************************************************/ 214 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 215 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 216 217 #endif /* TEGRA_DEF_H */ 218