1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_PRIVATE_H 8 #define TEGRA_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/psci/psci.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 18 #include <tegra_gic.h> 19 20 /******************************************************************************* 21 * Implementation defined ACTLR_EL1 bit definitions 22 ******************************************************************************/ 23 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 24 25 /******************************************************************************* 26 * Implementation defined ACTLR_EL2 bit definitions 27 ******************************************************************************/ 28 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 29 30 /******************************************************************************* 31 * Struct for parameters received from BL2 32 ******************************************************************************/ 33 typedef struct plat_params_from_bl2 { 34 /* TZ memory size */ 35 uint64_t tzdram_size; 36 /* TZ memory base */ 37 uint64_t tzdram_base; 38 /* UART port ID */ 39 int32_t uart_id; 40 /* L2 ECC parity protection disable flag */ 41 int32_t l2_ecc_parity_prot_dis; 42 /* SHMEM base address for storing the boot logs */ 43 uint64_t boot_profiler_shmem_base; 44 /* System Suspend Entry Firmware size */ 45 uint64_t sc7entry_fw_size; 46 /* System Suspend Entry Firmware base address */ 47 uint64_t sc7entry_fw_base; 48 } plat_params_from_bl2_t; 49 50 /******************************************************************************* 51 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 52 ******************************************************************************/ 53 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 54 55 /******************************************************************************* 56 * Struct describing parameters passed to bl31 57 ******************************************************************************/ 58 struct tegra_bl31_params { 59 param_header_t h; 60 image_info_t *bl31_image_info; 61 entry_point_info_t *bl32_ep_info; 62 image_info_t *bl32_image_info; 63 entry_point_info_t *bl33_ep_info; 64 image_info_t *bl33_image_info; 65 }; 66 67 /* Declarations for plat_psci_handlers.c */ 68 int32_t tegra_soc_validate_power_state(uint32_t power_state, 69 psci_power_state_t *req_state); 70 71 /* Declarations for plat_setup.c */ 72 const mmap_region_t *plat_get_mmio_map(void); 73 void plat_enable_console(int32_t id); 74 void plat_gic_setup(void); 75 struct tegra_bl31_params *plat_get_bl31_params(void); 76 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 77 void plat_early_platform_setup(void); 78 void plat_late_platform_setup(void); 79 80 /* Declarations for plat_secondary.c */ 81 void plat_secondary_setup(void); 82 int32_t plat_lock_cpu_vectors(void); 83 84 /* Declarations for tegra_fiq_glue.c */ 85 void tegra_fiq_handler_setup(void); 86 int tegra_fiq_get_intr_context(void); 87 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 88 89 /* Declarations for tegra_security.c */ 90 void tegra_security_setup(void); 91 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 92 93 /* Declarations for tegra_pm.c */ 94 void tegra_pm_system_suspend_entry(void); 95 void tegra_pm_system_suspend_exit(void); 96 int32_t tegra_system_suspended(void); 97 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 98 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 99 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 100 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 101 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 102 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 103 int32_t tegra_soc_prepare_system_reset(void); 104 __dead2 void tegra_soc_prepare_system_off(void); 105 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 106 const plat_local_state_t *states, 107 uint32_t ncpu); 108 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 109 void tegra_cpu_standby(plat_local_state_t cpu_state); 110 int32_t tegra_pwr_domain_on(u_register_t mpidr); 111 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 112 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 113 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 114 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 115 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 116 __dead2 void tegra_system_off(void); 117 __dead2 void tegra_system_reset(void); 118 int32_t tegra_validate_power_state(uint32_t power_state, 119 psci_power_state_t *req_state); 120 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 121 122 /* Declarations for tegraXXX_pm.c */ 123 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 124 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 125 126 /* Declarations for tegra_bl31_setup.c */ 127 plat_params_from_bl2_t *bl31_get_plat_params(void); 128 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 129 130 /* Declarations for tegra_delay_timer.c */ 131 void tegra_delay_timer_init(void); 132 133 void tegra_secure_entrypoint(void); 134 135 /* Declarations for tegra_sip_calls.c */ 136 uintptr_t tegra_sip_handler(uint32_t smc_fid, 137 u_register_t x1, 138 u_register_t x2, 139 u_register_t x3, 140 u_register_t x4, 141 void *cookie, 142 void *handle, 143 u_register_t flags); 144 int plat_sip_handler(uint32_t smc_fid, 145 uint64_t x1, 146 uint64_t x2, 147 uint64_t x3, 148 uint64_t x4, 149 const void *cookie, 150 void *handle, 151 uint64_t flags); 152 153 #endif /* TEGRA_PRIVATE_H */ 154