| fbde260b | 03-Apr-2023 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, tha
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, that
differs in the way the CPU cores' power and reset controls are handled.
This die variation can be detected by reading the SRAM version register.
Provide a predicate function that returns false if that die variant is
used. Since the CPU power control code is shared for all supported SoCs,
we provide an instance of this function for each SoC, as a static
inline, and return true on all other SoCs. This allows to always use
this function, and still let the compiler optimise away the unneeded
branch for those older SoCs.
This function is unused for now, but is needed in the next patch.
Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| b15e2cda | 09-Dec-2022 |
Mikhail Kalashnikov <iuncuim@gmail.com> |
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the o
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the original by using a different CPU control register IP block.
Add those newly used register offsets to the respective header file. The
MMIO block itself is actually present in both variants, though the
registers are different. The new registers tend to use one register per
core, in contrast to one register per cluster in the older revisions.
Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 9227719d | 14-Feb-2021 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Move sunxi_cpu_power_off_self() into platforms
The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new pl
allwinner: Move sunxi_cpu_power_off_self() into platforms
The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.
On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.
Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 49d98cd5 | 14-Dec-2020 |
Samuel Holland <samuel@sholland.org> |
allwinner: Add SPC security setup for H6
The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into
allwinner: Add SPC security setup for H6
The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5
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| 18fbfefb | 21-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Build PMIC bus drivers only in BL31
These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed bef
allwinner: Build PMIC bus drivers only in BL31
These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf
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| 818e6732 | 20-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Merge duplicate code in sunxi_power_down
The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matche
allwinner: Merge duplicate code in sunxi_power_down
The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().
The two error messages say essentially the same thing anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a
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| 4538c498 | 20-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Clean up PMIC-related error handling
- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in
allwinner: Clean up PMIC-related error handling
- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in error messages.
- Consistently omit the trailing period.
- No need to print the unknown SoC's ID, since we already did that
earlier in bl31_platform_setup().
- On the other hand, do print the ID of the unknown PMIC.
- Try to keep the messages concise, as the large string size in these
files was causing the firmware to spill into the next page.
- Downgrade the banner from NOTICE to INFO. It's purely informational,
and people should be using debug builds on untested hardware anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb
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| 7db0c960 | 27-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Use the arisc to turn off ARM cores
PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a co
allwinner: Use the arisc to turn off ARM cores
PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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