1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io> 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <errno.h> 9 10 #include <libfdt.h> 11 12 #include <platform_def.h> 13 14 #include <arch_helpers.h> 15 #include <common/debug.h> 16 #include <drivers/allwinner/sunxi_rsb.h> 17 #include <drivers/delay_timer.h> 18 #include <lib/mmio.h> 19 20 #include <sunxi_def.h> 21 #include <sunxi_mmap.h> 22 #include <sunxi_private.h> 23 24 static enum pmic_type { 25 UNKNOWN, 26 GENERIC_H5, 27 GENERIC_A64, 28 REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */ 29 AXP803_RSB, /* PMIC connected via RSB on most A64 boards */ 30 } pmic; 31 32 #define AXP803_HW_ADDR 0x3a3 33 #define AXP803_RT_ADDR 0x2d 34 35 /* 36 * On boards without a proper PMIC we struggle to turn off the system properly. 37 * Try to turn off as much off the system as we can, to reduce power 38 * consumption. This should be entered with only one core running and SMP 39 * disabled. 40 * This function only cares about peripherals. 41 */ 42 void sunxi_turn_off_soc(uint16_t socid) 43 { 44 int i; 45 46 /** Turn off most peripherals, most importantly DRAM users. **/ 47 /* Keep DRAM controller running for now. */ 48 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); 49 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); 50 /* Contains msgbox (bit 21) and spinlock (bit 22) */ 51 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0); 52 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0); 53 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0); 54 /* Keep PIO controller running for now. */ 55 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); 56 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0); 57 /* Contains UART0 (bit 16) */ 58 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0); 59 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0); 60 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0); 61 62 /** Turn off DRAM controller. **/ 63 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); 64 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); 65 66 /** Migrate CPU and bus clocks away from the PLLs. **/ 67 /* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */ 68 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000); 69 /* APB2: use OSC24M */ 70 mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000); 71 /* AHB2: use AHB1 clock */ 72 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0); 73 /* CPU: use OSC24M */ 74 mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000); 75 76 /** Turn off PLLs. **/ 77 for (i = 0; i < 6; i++) 78 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); 79 switch (socid) { 80 case SUNXI_SOC_H5: 81 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); 82 break; 83 case SUNXI_SOC_A64: 84 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); 85 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); 86 break; 87 } 88 } 89 90 static int rsb_init(void) 91 { 92 int ret; 93 94 ret = rsb_init_controller(); 95 if (ret) 96 return ret; 97 98 /* Start with 400 KHz to issue the I2C->RSB switch command. */ 99 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000); 100 if (ret) 101 return ret; 102 103 /* 104 * Initiate an I2C transaction to write 0x7c into register 0x3e, 105 * switching the PMIC to RSB mode. 106 */ 107 ret = rsb_set_device_mode(0x7c3e00); 108 if (ret) 109 return ret; 110 111 /* Now in RSB mode, switch to the recommended 3 MHz. */ 112 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); 113 if (ret) 114 return ret; 115 116 /* Associate the 8-bit runtime address with the 12-bit bus address. */ 117 return rsb_assign_runtime_address(AXP803_HW_ADDR, 118 AXP803_RT_ADDR); 119 } 120 121 static int axp_write(uint8_t reg, uint8_t val) 122 { 123 return rsb_write(AXP803_RT_ADDR, reg, val); 124 } 125 126 static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) 127 { 128 uint8_t regval; 129 int ret; 130 131 ret = rsb_read(AXP803_RT_ADDR, reg); 132 if (ret < 0) 133 return ret; 134 135 regval = (ret & ~clr_mask) | set_mask; 136 137 return rsb_write(AXP803_RT_ADDR, reg, regval); 138 } 139 140 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) 141 #define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) 142 143 static bool should_enable_regulator(const void *fdt, int node) 144 { 145 if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) 146 return true; 147 if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) 148 return true; 149 return false; 150 } 151 152 /* 153 * Retrieve the voltage from a given regulator DTB node. 154 * Both the regulator-{min,max}-microvolt properties must be present and 155 * have the same value. Return that value in millivolts. 156 */ 157 static int fdt_get_regulator_millivolt(const void *fdt, int node) 158 { 159 const fdt32_t *prop; 160 uint32_t min_volt; 161 162 prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); 163 if (prop == NULL) 164 return -EINVAL; 165 min_volt = fdt32_to_cpu(*prop); 166 167 prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); 168 if (prop == NULL) 169 return -EINVAL; 170 171 if (fdt32_to_cpu(*prop) != min_volt) 172 return -EINVAL; 173 174 return min_volt / 1000; 175 } 176 177 #define NO_SPLIT 0xff 178 179 static const struct axp_regulator { 180 char *dt_name; 181 uint16_t min_volt; 182 uint16_t max_volt; 183 uint16_t step; 184 unsigned char split; 185 unsigned char volt_reg; 186 unsigned char switch_reg; 187 unsigned char switch_bit; 188 } regulators[] = { 189 {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0}, 190 {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, 191 {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5}, 192 {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, 193 {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, 194 {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, 195 {"dldo4", 700, 3300, 100, NO_SPLIT, 0x18, 0x12, 6}, 196 {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, 197 {} 198 }; 199 200 static int setup_regulator(const void *fdt, int node, 201 const struct axp_regulator *reg) 202 { 203 int mvolt; 204 uint8_t regval; 205 206 if (!should_enable_regulator(fdt, node)) 207 return -ENOENT; 208 209 mvolt = fdt_get_regulator_millivolt(fdt, node); 210 if (mvolt < reg->min_volt || mvolt > reg->max_volt) 211 return -EINVAL; 212 213 regval = (mvolt / reg->step) - (reg->min_volt / reg->step); 214 if (regval > reg->split) 215 regval = ((regval - reg->split) / 2) + reg->split; 216 217 axp_write(reg->volt_reg, regval); 218 if (reg->switch_reg < 0xff) 219 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); 220 221 INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name, 222 mvolt / 1000, mvolt % 1000); 223 224 return 0; 225 } 226 227 static void setup_axp803_rails(const void *fdt) 228 { 229 int node; 230 bool dc1sw = false; 231 232 /* locate the PMIC DT node, bail out if not found */ 233 node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); 234 if (node < 0) { 235 WARN("PMIC: No PMIC DT node, skipping setup\n"); 236 return; 237 } 238 239 if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) { 240 axp_clrbits(0x8f, BIT(4)); 241 axp_setbits(0x30, BIT(2)); 242 INFO("PMIC: AXP803: Enabling DRIVEVBUS\n"); 243 } 244 245 /* descend into the "regulators" subnode */ 246 node = fdt_subnode_offset(fdt, node, "regulators"); 247 if (node < 0) { 248 WARN("PMIC: No regulators DT node, skipping setup\n"); 249 return; 250 } 251 252 /* iterate over all regulators to find used ones */ 253 for (node = fdt_first_subnode(fdt, node); 254 node >= 0; 255 node = fdt_next_subnode(fdt, node)) { 256 const struct axp_regulator *reg; 257 const char *name; 258 int length; 259 260 /* We only care if it's always on or referenced. */ 261 if (!should_enable_regulator(fdt, node)) 262 continue; 263 264 name = fdt_get_name(fdt, node, &length); 265 for (reg = regulators; reg->dt_name; reg++) { 266 if (!strncmp(name, reg->dt_name, length)) { 267 setup_regulator(fdt, node, reg); 268 break; 269 } 270 } 271 272 if (!strncmp(name, "dc1sw", length)) { 273 /* Delay DC1SW enablement to avoid overheating. */ 274 dc1sw = true; 275 continue; 276 } 277 } 278 279 /* 280 * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts 281 * down. So always enable DC1SW as the very last regulator. 282 */ 283 if (dc1sw) { 284 INFO("PMIC: AXP803: Enabling DC1SW\n"); 285 axp_setbits(0x12, BIT(7)); 286 } 287 } 288 289 int sunxi_pmic_setup(uint16_t socid, const void *fdt) 290 { 291 int ret; 292 293 switch (socid) { 294 case SUNXI_SOC_H5: 295 NOTICE("PMIC: Assuming H5 reference regulator design\n"); 296 297 pmic = REF_DESIGN_H5; 298 299 break; 300 case SUNXI_SOC_A64: 301 pmic = GENERIC_A64; 302 303 INFO("PMIC: Probing AXP803 on RSB\n"); 304 305 ret = sunxi_init_platform_r_twi(socid, true); 306 if (ret) 307 return ret; 308 309 ret = rsb_init(); 310 if (ret) 311 return ret; 312 313 pmic = AXP803_RSB; 314 315 if (fdt) 316 setup_axp803_rails(fdt); 317 318 break; 319 default: 320 return -ENODEV; 321 } 322 return 0; 323 } 324 325 void sunxi_power_down(void) 326 { 327 switch (pmic) { 328 case GENERIC_H5: 329 /* Turn off as many peripherals and clocks as we can. */ 330 sunxi_turn_off_soc(SUNXI_SOC_H5); 331 /* Turn off the pin controller now. */ 332 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 333 break; 334 case GENERIC_A64: 335 /* Turn off as many peripherals and clocks as we can. */ 336 sunxi_turn_off_soc(SUNXI_SOC_A64); 337 /* Turn off the pin controller now. */ 338 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 339 break; 340 case REF_DESIGN_H5: 341 sunxi_turn_off_soc(SUNXI_SOC_H5); 342 343 /* 344 * Switch PL pins to power off the board: 345 * - PL5 (VCC_IO) -> high 346 * - PL8 (PWR-STB = CPU power supply) -> low 347 * - PL9 (PWR-DRAM) ->low 348 * - PL10 (power LED) -> low 349 * Note: Clearing PL8 will reset the board, so keep it up. 350 */ 351 sunxi_set_gpio_out('L', 5, 1); 352 sunxi_set_gpio_out('L', 9, 0); 353 sunxi_set_gpio_out('L', 10, 0); 354 355 /* Turn off pin controller now. */ 356 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 357 358 break; 359 case AXP803_RSB: 360 /* (Re-)init RSB in case the rich OS has disabled it. */ 361 sunxi_init_platform_r_twi(SUNXI_SOC_A64, true); 362 rsb_init(); 363 364 /* Set "power disable control" bit */ 365 axp_setbits(0x32, BIT(7)); 366 break; 367 default: 368 break; 369 } 370 371 } 372