| 793c38f0 | 24-Oct-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: power: Add DCDC6 power rail
The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is
on by default and uses the default voltage.
As there seems to be at least on board usin
allwinner: power: Add DCDC6 power rail
The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is
on by default and uses the default voltage.
As there seems to be at least on board using a different voltage, add
the rail to the list of known voltage lines, so we can setup the right
voltage as early as possible.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| a561e41b | 24-Oct-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: power: add enable switches for DCDC1/5
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every b
allwinner: power: add enable switches for DCDC1/5
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.
Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| d93eb446 | 05-Nov-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default,
allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 7db0c960 | 27-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Use the arisc to turn off ARM cores
PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a co
allwinner: Use the arisc to turn off ARM cores
PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| ccd3ab2d | 19-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: PMIC: AXP803: Delay activation of DC1SW switch
There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To
allwinner: PMIC: AXP803: Delay activation of DC1SW switch
There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| fb4e9786 | 16-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main
allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| ed80c1e2 | 16-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Scan AXP803 FDT node to setup initial power rails
Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compati
allwinner: Scan AXP803 FDT node to setup initial power rails
Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compatible string to find the PMIC node.
- We switch the N_VBUSEN pin if the DT property tells us so.
- We scan over all regulator subnodes, and switch DC1SW if there is at
least one other node referencing it (judging by the existence of a
phandle property in that subnode).
This is just the first part of the setup, a follow up patch will setup
voltages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| eae5fe79 | 15-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: A64: Add AXP803 PMIC support to power off the board
Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.
Use th
allwinner: A64: Add AXP803 PMIC support to power off the board
Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.
Use the newly introduced RSB driver to detect and program the PMIC on
boot, then later to turn off the main voltage rails when receiving a
PSCI SYSTEM_POWER_OFF command.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 3d22228f | 01-Oct-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: H5: Implement power down for H5 reference design boards
Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulat
allwinner: H5: Implement power down for H5 reference design boards
Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulators which are
controlled by the same PortL GPIO pins to power the ARM CPU cores, the
DRAM and the I/O ports.
Add a SoC specific power down routine, which turns those regulators off
when ATF detects running on an H5 SoC and the rich OS triggers a
SYSTEM_POWEROFF PSCI call.
NOTE: It sounds very tempting to turn the CPU power off, but this is not
working as expected, instead the system is rebooting. Most probably this
is due to VCC-SYS also being controlled by the same GPIO line, and
turning this off requires an elaborate and not fully understood setup.
Apparently not even Allwinner reference code is turning this regulator
off. So for now we refrain to pulling down PL8, the power consumption is
quite low anyway, so we are as close to poweroff as reasonably possible.
Many thanks to Samuel for doing some research on that topic.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 4ec1a239 | 14-Oct-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Export sunxi_private.h
So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will
allwinner: Export sunxi_private.h
So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.
So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.
This will be used in follow up patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| f953c30f | 01-Oct-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: A64/H5: Add basic and generic shutdown method
Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
cl
allwinner: A64/H5: Add basic and generic shutdown method
Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
clocks as possible, so that the power consumption is reduced. Then
halt the last core, as before.
This will later be extended with proper PMIC support for supported
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| c3af6b00 | 20-Sep-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Adjust memory mapping to fit into 256MB
At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if
allwinner: Adjust memory mapping to fit into 256MB
At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).
To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| acb8b3ca | 01-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Add security setup
Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure w
allwinner: Add security setup
Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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