1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io> 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <allwinner/sunxi_rsb.h> 9 #include <arch_helpers.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <errno.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform_def.h> 16 #include <sunxi_def.h> 17 #include <sunxi_mmap.h> 18 #include <sunxi_private.h> 19 20 static enum pmic_type { 21 GENERIC_H5, 22 GENERIC_A64, 23 REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */ 24 AXP803_RSB, /* PMIC connected via RSB on most A64 boards */ 25 } pmic; 26 27 #define AXP803_HW_ADDR 0x3a3 28 #define AXP803_RT_ADDR 0x2d 29 30 /* 31 * On boards without a proper PMIC we struggle to turn off the system properly. 32 * Try to turn off as much off the system as we can, to reduce power 33 * consumption. This should be entered with only one core running and SMP 34 * disabled. 35 * This function only cares about peripherals. 36 */ 37 void sunxi_turn_off_soc(uint16_t socid) 38 { 39 int i; 40 41 /** Turn off most peripherals, most importantly DRAM users. **/ 42 /* Keep DRAM controller running for now. */ 43 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); 44 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); 45 /* Contains msgbox (bit 21) and spinlock (bit 22) */ 46 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0); 47 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0); 48 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0); 49 /* Keep PIO controller running for now. */ 50 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); 51 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0); 52 /* Contains UART0 (bit 16) */ 53 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0); 54 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0); 55 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0); 56 57 /** Turn off DRAM controller. **/ 58 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); 59 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); 60 61 /** Migrate CPU and bus clocks away from the PLLs. **/ 62 /* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */ 63 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000); 64 /* APB2: use OSC24M */ 65 mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000); 66 /* AHB2: use AHB1 clock */ 67 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0); 68 /* CPU: use OSC24M */ 69 mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000); 70 71 /** Turn off PLLs. **/ 72 for (i = 0; i < 6; i++) 73 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); 74 switch (socid) { 75 case SUNXI_SOC_H5: 76 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); 77 break; 78 case SUNXI_SOC_A64: 79 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); 80 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); 81 break; 82 } 83 } 84 85 static int rsb_init(void) 86 { 87 int ret; 88 89 ret = rsb_init_controller(); 90 if (ret) 91 return ret; 92 93 /* Start with 400 KHz to issue the I2C->RSB switch command. */ 94 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000); 95 if (ret) 96 return ret; 97 98 /* 99 * Initiate an I2C transaction to write 0x7c into register 0x3e, 100 * switching the PMIC to RSB mode. 101 */ 102 ret = rsb_set_device_mode(0x7c3e00); 103 if (ret) 104 return ret; 105 106 /* Now in RSB mode, switch to the recommended 3 MHz. */ 107 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); 108 if (ret) 109 return ret; 110 111 /* Associate the 8-bit runtime address with the 12-bit bus address. */ 112 return rsb_assign_runtime_address(AXP803_HW_ADDR, 113 AXP803_RT_ADDR); 114 } 115 116 static int axp_setbits(uint8_t reg, uint8_t set_mask) 117 { 118 uint8_t regval; 119 int ret; 120 121 ret = rsb_read(AXP803_RT_ADDR, reg); 122 if (ret < 0) 123 return ret; 124 125 regval = ret | set_mask; 126 127 return rsb_write(AXP803_RT_ADDR, reg, regval); 128 } 129 130 static bool should_enable_regulator(const void *fdt, int node) 131 { 132 if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) 133 return true; 134 if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) 135 return true; 136 return false; 137 } 138 139 static void setup_axp803_rails(const void *fdt) 140 { 141 int node; 142 143 /* locate the PMIC DT node, bail out if not found */ 144 node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); 145 if (node == -FDT_ERR_NOTFOUND) { 146 WARN("BL31: PMIC: No AXP803 DT node, skipping initial setup.\n"); 147 return; 148 } 149 150 if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) 151 axp_setbits(0x8f, BIT(4)); 152 153 /* descend into the "regulators" subnode */ 154 node = fdt_first_subnode(fdt, node); 155 156 /* iterate over all regulators to find used ones */ 157 for (node = fdt_first_subnode(fdt, node); 158 node != -FDT_ERR_NOTFOUND; 159 node = fdt_next_subnode(fdt, node)) { 160 const char *name; 161 int length; 162 163 /* We only care if it's always on or referenced. */ 164 if (!should_enable_regulator(fdt, node)) 165 continue; 166 167 name = fdt_get_name(fdt, node, &length); 168 if (!strncmp(name, "dc1sw", length)) { 169 INFO("PMIC: AXP803: Enabling DC1SW\n"); 170 axp_setbits(0x12, BIT(7)); 171 continue; 172 } 173 } 174 } 175 176 int sunxi_pmic_setup(uint16_t socid, const void *fdt) 177 { 178 int ret; 179 180 switch (socid) { 181 case SUNXI_SOC_H5: 182 pmic = REF_DESIGN_H5; 183 NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n"); 184 break; 185 case SUNXI_SOC_A64: 186 pmic = GENERIC_A64; 187 ret = sunxi_init_platform_r_twi(socid, true); 188 if (ret) 189 return ret; 190 191 ret = rsb_init(); 192 if (ret) 193 return ret; 194 195 pmic = AXP803_RSB; 196 NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n"); 197 198 if (fdt) 199 setup_axp803_rails(fdt); 200 201 break; 202 default: 203 NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid); 204 return -ENODEV; 205 } 206 return 0; 207 } 208 209 void __dead2 sunxi_power_down(void) 210 { 211 switch (pmic) { 212 case GENERIC_H5: 213 /* Turn off as many peripherals and clocks as we can. */ 214 sunxi_turn_off_soc(SUNXI_SOC_H5); 215 /* Turn off the pin controller now. */ 216 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 217 break; 218 case GENERIC_A64: 219 /* Turn off as many peripherals and clocks as we can. */ 220 sunxi_turn_off_soc(SUNXI_SOC_A64); 221 /* Turn off the pin controller now. */ 222 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 223 break; 224 case REF_DESIGN_H5: 225 sunxi_turn_off_soc(SUNXI_SOC_H5); 226 227 /* 228 * Switch PL pins to power off the board: 229 * - PL5 (VCC_IO) -> high 230 * - PL8 (PWR-STB = CPU power supply) -> low 231 * - PL9 (PWR-DRAM) ->low 232 * - PL10 (power LED) -> low 233 * Note: Clearing PL8 will reset the board, so keep it up. 234 */ 235 sunxi_set_gpio_out('L', 5, 1); 236 sunxi_set_gpio_out('L', 9, 0); 237 sunxi_set_gpio_out('L', 10, 0); 238 239 /* Turn off pin controller now. */ 240 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 241 242 break; 243 case AXP803_RSB: 244 /* (Re-)init RSB in case the rich OS has disabled it. */ 245 sunxi_init_platform_r_twi(SUNXI_SOC_A64, true); 246 rsb_init(); 247 248 /* Set "power disable control" bit */ 249 axp_setbits(0x32, BIT(7)); 250 break; 251 default: 252 break; 253 } 254 255 udelay(1000); 256 ERROR("PSCI: Cannot turn off system, halting.\n"); 257 wfi(); 258 panic(); 259 } 260