| c72f4d4c | 21-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set t
ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| f9d7e17e | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: update DRAM init code for LD20 SoC
Import the latest version from the Diag software.
- Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for bo
ARM: uniphier: update DRAM init code for LD20 SoC
Import the latest version from the Diag software.
- Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 682e09ff | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use.
Signed-off-by: M
ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| fcc238ba | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: collect clock/PLL init code into a single directory
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory
ARM: uniphier: collect clock/PLL init code into a single directory
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 6a3e4274 | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move PLL init code to U-Boot proper where possible
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to
ARM: uniphier: move PLL init code to U-Boot proper where possible
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| b78ffc53 | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20
This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely.
Signed-off-by: Ma
ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20
This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 5ac9dfbe | 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: consolidate NAND pin-mux settings
The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl
ARM: uniphier: consolidate NAND pin-mux settings
The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| f6bbec3d | 13-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21
Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM i
ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21
Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| b2916712 | 13-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: merge board init functions into board_init()
Currently, the UniPhier platform calls several init functions in the following order:
[1] spl_board_init() [2] board_early_init_f()
ARM: uniphier: merge board init functions into board_init()
Currently, the UniPhier platform calls several init functions in the following order:
[1] spl_board_init() [2] board_early_init_f() [3] board_init() [4] board_early_init_r() [5] board_late_init()
The serial console is not ready at the point of [2], so we want to avoid using [2] from the view point of debuggability. Fortunately, all of the initialization in [2] can be delayed until [3]. I see no good reason to split into [3] and [4]. So, merge [2] through [4].
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 43a8cc90 | 13-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: use checkboard() instead of misc_init_f()
We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose.
Signed-off-by: Masa
ARM: uniphier: use checkboard() instead of misc_init_f()
We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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