1 /* 2 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 #ifndef __CONFIGS_MXS_H__ 20 #define __CONFIGS_MXS_H__ 21 22 /* 23 * Includes 24 */ 25 26 #if defined(CONFIG_MX23) && defined(CONFIG_MX28) 27 #error Select either CONFIG_MX23 or CONFIG_MX28 , never both! 28 #elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) 29 #error Select one of CONFIG_MX23 or CONFIG_MX28 ! 30 #endif 31 32 #include <asm/arch/regs-base.h> 33 34 #if defined(CONFIG_MX23) 35 #include <asm/arch/iomux-mx23.h> 36 #elif defined(CONFIG_MX28) 37 #include <asm/arch/iomux-mx28.h> 38 #endif 39 40 /* 41 * CPU specifics 42 */ 43 44 /* Startup hooks */ 45 #define CONFIG_BOARD_EARLY_INIT_F 46 #define CONFIG_ARCH_MISC_INIT 47 48 /* SPL */ 49 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE 50 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" 51 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" 52 #define CONFIG_SPL_SERIAL_SUPPORT 53 54 /* Memory sizes */ 55 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ 56 #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ 57 #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ 58 59 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ 60 #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 61 #if defined(CONFIG_MX23) 62 #define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) 63 #elif defined(CONFIG_MX28) 64 #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) 65 #endif 66 67 /* Point initial SP in SRAM so SPL can use it too. */ 68 #define CONFIG_SYS_INIT_SP_OFFSET \ 69 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 70 #define CONFIG_SYS_INIT_SP_ADDR \ 71 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 72 73 /* 74 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some 75 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot 76 * binary. In case there was more of this mess, 0x100 bytes are skipped. 77 * 78 * In case of a HAB boot, we cannot for some weird reason use the first 4KiB 79 * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST 80 * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. 81 * 82 * As for the SPL, we must avoid the first 4 KiB as well, but we load the 83 * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. 84 */ 85 #define CONFIG_SYS_TEXT_BASE 0x40002000 86 #define CONFIG_SPL_TEXT_BASE 0x00001000 87 88 /* U-Boot general configuration */ 89 #define CONFIG_SYS_LONGHELP 90 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 91 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 93 /* Boot argument buffer size */ 94 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 95 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 96 97 /* Booting Linux */ 98 #define CONFIG_CMDLINE_TAG 99 #define CONFIG_SETUP_MEMORY_TAGS 100 101 /* 102 * Drivers 103 */ 104 105 /* APBH DMA */ 106 #define CONFIG_APBH_DMA 107 108 /* GPIO */ 109 #define CONFIG_MXS_GPIO 110 111 /* 112 * DUART Serial Driver. 113 * Conflicts with AUART driver which can be set by board. 114 */ 115 #define CONFIG_PL011_SERIAL 116 #define CONFIG_PL011_CLOCK 24000000 117 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } 118 #define CONFIG_CONS_INDEX 0 119 /* Default baudrate can be overridden by board! */ 120 #ifndef CONFIG_BAUDRATE 121 #define CONFIG_BAUDRATE 115200 122 #endif 123 124 /* FEC Ethernet on SoC */ 125 #ifdef CONFIG_FEC_MXC 126 #define CONFIG_MII 127 #ifndef CONFIG_ETHPRIME 128 #define CONFIG_ETHPRIME "FEC0" 129 #endif 130 #ifndef CONFIG_FEC_XCV_TYPE 131 #define CONFIG_FEC_XCV_TYPE RMII 132 #endif 133 #endif 134 135 /* I2C */ 136 #ifdef CONFIG_CMD_I2C 137 #define CONFIG_SYS_I2C 138 #define CONFIG_SYS_I2C_MXS 139 #define CONFIG_HARD_I2C 140 #ifndef CONFIG_SYS_I2C_SPEED 141 #define CONFIG_SYS_I2C_SPEED 400000 142 #endif 143 #endif 144 145 /* LCD */ 146 #ifdef CONFIG_VIDEO 147 #define CONFIG_CFB_CONSOLE 148 #define CONFIG_VIDEO_MXS 149 #define CONFIG_VIDEO_SW_CURSOR 150 #define CONFIG_VGA_AS_SINGLE_DEVICE 151 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 152 #endif 153 154 /* MMC */ 155 #ifdef CONFIG_CMD_MMC 156 #define CONFIG_MMC 157 #define CONFIG_GENERIC_MMC 158 #define CONFIG_BOUNCE_BUFFER 159 #define CONFIG_MXS_MMC 160 #endif 161 162 /* NAND */ 163 #ifdef CONFIG_CMD_NAND 164 #define CONFIG_NAND_MXS 165 #define CONFIG_SYS_MAX_NAND_DEVICE 1 166 #define CONFIG_SYS_NAND_BASE 0x60000000 167 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 168 #endif 169 170 /* OCOTP */ 171 #ifdef CONFIG_CMD_FUSE 172 #define CONFIG_MXS_OCOTP 173 #endif 174 175 /* SPI */ 176 #ifdef CONFIG_CMD_SPI 177 #define CONFIG_HARD_SPI 178 #define CONFIG_MXS_SPI 179 #define CONFIG_SPI_HALF_DUPLEX 180 #endif 181 182 /* USB */ 183 #ifdef CONFIG_CMD_USB 184 #define CONFIG_USB_EHCI 185 #define CONFIG_USB_EHCI_MXS 186 #define CONFIG_EHCI_IS_TDI 187 #endif 188 189 #endif /* __CONFIGS_MXS_H__ */ 190