1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 71 #define CONFIG_SPL_WATCHDOG_SUPPORT 72 #define CONFIG_SPL_SERIAL_SUPPORT 73 #define CONFIG_SPL_MMC_SUPPORT 74 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 75 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 76 77 #define CONFIG_SPL_TEXT_BASE 0x10000000 78 #define CONFIG_SPL_MAX_SIZE 0x1a000 79 #define CONFIG_SPL_STACK 0x1001d000 80 #define CONFIG_SPL_PAD_TO 0x1c000 81 #define CONFIG_SYS_TEXT_BASE 0x82000000 82 83 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 84 CONFIG_SYS_MONITOR_LEN) 85 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 86 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 87 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 88 #define CONFIG_SYS_MONITOR_LEN 0xc0000 89 #endif 90 91 #ifdef CONFIG_QSPI_BOOT 92 #define CONFIG_SYS_TEXT_BASE 0x40010000 93 #endif 94 95 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 96 #define CONFIG_SYS_NO_FLASH 97 #endif 98 99 #ifdef CONFIG_NAND_BOOT 100 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 101 #define CONFIG_SPL_FRAMEWORK 102 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 103 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 104 #define CONFIG_SPL_WATCHDOG_SUPPORT 105 #define CONFIG_SPL_SERIAL_SUPPORT 106 #define CONFIG_SPL_NAND_SUPPORT 107 108 #define CONFIG_SPL_TEXT_BASE 0x10000000 109 #define CONFIG_SPL_MAX_SIZE 0x1a000 110 #define CONFIG_SPL_STACK 0x1001d000 111 #define CONFIG_SPL_PAD_TO 0x1c000 112 #define CONFIG_SYS_TEXT_BASE 0x82000000 113 114 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 115 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 116 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 117 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 119 120 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 121 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 122 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 123 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 124 #define CONFIG_SYS_MONITOR_LEN 0x80000 125 #endif 126 127 #ifndef CONFIG_SYS_TEXT_BASE 128 #define CONFIG_SYS_TEXT_BASE 0x60100000 129 #endif 130 131 #define CONFIG_NR_DRAM_BANKS 1 132 133 #define CONFIG_DDR_SPD 134 #define SPD_EEPROM_ADDRESS 0x51 135 #define CONFIG_SYS_SPD_BUS_NUM 0 136 137 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 138 #ifndef CONFIG_SYS_FSL_DDR4 139 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 140 #define CONFIG_SYS_DDR_RAW_TIMING 141 #endif 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 144 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 #define CONFIG_DDR_ECC 149 #ifdef CONFIG_DDR_ECC 150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 151 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 152 #endif 153 154 #define CONFIG_SYS_HAS_SERDES 155 156 #define CONFIG_FSL_CAAM /* Enable CAAM */ 157 158 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 159 !defined(CONFIG_QSPI_BOOT) 160 #define CONFIG_U_QE 161 #endif 162 163 /* 164 * IFC Definitions 165 */ 166 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 167 #define CONFIG_FSL_IFC 168 #define CONFIG_SYS_FLASH_BASE 0x60000000 169 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 170 171 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 172 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 173 CSPR_PORT_SIZE_16 | \ 174 CSPR_MSEL_NOR | \ 175 CSPR_V) 176 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 177 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 178 + 0x8000000) | \ 179 CSPR_PORT_SIZE_16 | \ 180 CSPR_MSEL_NOR | \ 181 CSPR_V) 182 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 183 184 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 185 CSOR_NOR_TRHZ_80) 186 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 187 FTIM0_NOR_TEADC(0x5) | \ 188 FTIM0_NOR_TEAHC(0x5)) 189 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 190 FTIM1_NOR_TRAD_NOR(0x1a) | \ 191 FTIM1_NOR_TSEQRAD_NOR(0x13)) 192 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 193 FTIM2_NOR_TCH(0x4) | \ 194 FTIM2_NOR_TWPH(0xe) | \ 195 FTIM2_NOR_TWP(0x1c)) 196 #define CONFIG_SYS_NOR_FTIM3 0 197 198 #define CONFIG_FLASH_CFI_DRIVER 199 #define CONFIG_SYS_FLASH_CFI 200 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 201 #define CONFIG_SYS_FLASH_QUIET_TEST 202 #define CONFIG_FLASH_SHOW_PROGRESS 45 203 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 204 #define CONFIG_SYS_WRITE_SWAPPED_DATA 205 206 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 207 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210 211 #define CONFIG_SYS_FLASH_EMPTY_INFO 212 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 213 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 214 215 /* 216 * NAND Flash Definitions 217 */ 218 #define CONFIG_NAND_FSL_IFC 219 220 #define CONFIG_SYS_NAND_BASE 0x7e800000 221 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 222 223 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 224 225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 226 | CSPR_PORT_SIZE_8 \ 227 | CSPR_MSEL_NAND \ 228 | CSPR_V) 229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 230 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 231 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 232 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 233 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 234 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 235 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 236 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 237 238 #define CONFIG_SYS_NAND_ONFI_DETECTION 239 240 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 241 FTIM0_NAND_TWP(0x18) | \ 242 FTIM0_NAND_TWCHT(0x7) | \ 243 FTIM0_NAND_TWH(0xa)) 244 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 245 FTIM1_NAND_TWBE(0x39) | \ 246 FTIM1_NAND_TRR(0xe) | \ 247 FTIM1_NAND_TRP(0x18)) 248 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 249 FTIM2_NAND_TREH(0xa) | \ 250 FTIM2_NAND_TWHRE(0x1e)) 251 #define CONFIG_SYS_NAND_FTIM3 0x0 252 253 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 254 #define CONFIG_SYS_MAX_NAND_DEVICE 1 255 #define CONFIG_CMD_NAND 256 257 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 258 #endif 259 260 /* 261 * QIXIS Definitions 262 */ 263 #define CONFIG_FSL_QIXIS 264 265 #ifdef CONFIG_FSL_QIXIS 266 #define QIXIS_BASE 0x7fb00000 267 #define QIXIS_BASE_PHYS QIXIS_BASE 268 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 269 #define QIXIS_LBMAP_SWITCH 6 270 #define QIXIS_LBMAP_MASK 0x0f 271 #define QIXIS_LBMAP_SHIFT 0 272 #define QIXIS_LBMAP_DFLTBANK 0x00 273 #define QIXIS_LBMAP_ALTBANK 0x04 274 #define QIXIS_PWR_CTL 0x21 275 #define QIXIS_PWR_CTL_POWEROFF 0x80 276 #define QIXIS_RST_CTL_RESET 0x44 277 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 278 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 279 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 280 281 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 282 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 283 CSPR_PORT_SIZE_8 | \ 284 CSPR_MSEL_GPCM | \ 285 CSPR_V) 286 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 287 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 288 CSOR_NOR_NOR_MODE_AVD_NOR | \ 289 CSOR_NOR_TRHZ_80) 290 291 /* 292 * QIXIS Timing parameters for IFC GPCM 293 */ 294 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 295 FTIM0_GPCM_TEADC(0xe) | \ 296 FTIM0_GPCM_TEAHC(0xe)) 297 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 298 FTIM1_GPCM_TRAD(0x1f)) 299 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 300 FTIM2_GPCM_TCH(0xe) | \ 301 FTIM2_GPCM_TWP(0xf0)) 302 #define CONFIG_SYS_FPGA_FTIM3 0x0 303 #endif 304 305 #if defined(CONFIG_NAND_BOOT) 306 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 307 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 308 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 309 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 310 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 311 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 312 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 313 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 314 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 323 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 324 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 331 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 332 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 333 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 334 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 335 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 336 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 337 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 338 #else 339 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 340 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 341 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 342 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 343 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 344 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 345 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 346 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 347 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 348 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 349 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 355 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 356 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 357 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 358 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 359 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 360 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 361 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 362 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 363 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 364 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 365 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 366 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 367 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 368 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 369 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 370 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 371 #endif 372 373 /* 374 * Serial Port 375 */ 376 #ifdef CONFIG_LPUART 377 #define CONFIG_LPUART_32B_REG 378 #else 379 #define CONFIG_CONS_INDEX 1 380 #define CONFIG_SYS_NS16550_SERIAL 381 #ifndef CONFIG_DM_SERIAL 382 #define CONFIG_SYS_NS16550_REG_SIZE 1 383 #endif 384 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 385 #endif 386 387 #define CONFIG_BAUDRATE 115200 388 389 /* 390 * I2C 391 */ 392 #define CONFIG_SYS_I2C 393 #define CONFIG_SYS_I2C_MXC 394 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 395 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 396 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 397 398 /* 399 * I2C bus multiplexer 400 */ 401 #define I2C_MUX_PCA_ADDR_PRI 0x77 402 #define I2C_MUX_CH_DEFAULT 0x8 403 #define I2C_MUX_CH_CH7301 0xC 404 405 /* 406 * MMC 407 */ 408 #define CONFIG_MMC 409 #define CONFIG_FSL_ESDHC 410 #define CONFIG_GENERIC_MMC 411 412 #define CONFIG_DOS_PARTITION 413 414 /* SPI */ 415 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 416 /* QSPI */ 417 #define QSPI0_AMBA_BASE 0x40000000 418 #define FSL_QSPI_FLASH_SIZE (1 << 24) 419 #define FSL_QSPI_FLASH_NUM 2 420 421 /* DSPI */ 422 423 /* DM SPI */ 424 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 425 #define CONFIG_DM_SPI_FLASH 426 #define CONFIG_SPI_FLASH_DATAFLASH 427 #endif 428 #endif 429 430 /* 431 * USB 432 */ 433 /* EHCI Support - disbaled by default */ 434 /*#define CONFIG_HAS_FSL_DR_USB*/ 435 436 #ifdef CONFIG_HAS_FSL_DR_USB 437 #define CONFIG_USB_EHCI 438 #define CONFIG_USB_EHCI_FSL 439 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 440 #endif 441 442 /*XHCI Support - enabled by default*/ 443 #define CONFIG_HAS_FSL_XHCI_USB 444 445 #ifdef CONFIG_HAS_FSL_XHCI_USB 446 #define CONFIG_USB_XHCI_FSL 447 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 448 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 449 #endif 450 451 /* 452 * Video 453 */ 454 #define CONFIG_FSL_DCU_FB 455 456 #ifdef CONFIG_FSL_DCU_FB 457 #define CONFIG_VIDEO 458 #define CONFIG_CMD_BMP 459 #define CONFIG_CFB_CONSOLE 460 #define CONFIG_VGA_AS_SINGLE_DEVICE 461 #define CONFIG_VIDEO_LOGO 462 #define CONFIG_VIDEO_BMP_LOGO 463 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 464 465 #define CONFIG_FSL_DIU_CH7301 466 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 467 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 468 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 469 #endif 470 471 /* 472 * eTSEC 473 */ 474 #define CONFIG_TSEC_ENET 475 476 #ifdef CONFIG_TSEC_ENET 477 #define CONFIG_MII 478 #define CONFIG_MII_DEFAULT_TSEC 3 479 #define CONFIG_TSEC1 1 480 #define CONFIG_TSEC1_NAME "eTSEC1" 481 #define CONFIG_TSEC2 1 482 #define CONFIG_TSEC2_NAME "eTSEC2" 483 #define CONFIG_TSEC3 1 484 #define CONFIG_TSEC3_NAME "eTSEC3" 485 486 #define TSEC1_PHY_ADDR 1 487 #define TSEC2_PHY_ADDR 2 488 #define TSEC3_PHY_ADDR 3 489 490 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 491 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 492 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 493 494 #define TSEC1_PHYIDX 0 495 #define TSEC2_PHYIDX 0 496 #define TSEC3_PHYIDX 0 497 498 #define CONFIG_ETHPRIME "eTSEC1" 499 500 #define CONFIG_PHY_GIGE 501 #define CONFIG_PHYLIB 502 #define CONFIG_PHY_REALTEK 503 504 #define CONFIG_HAS_ETH0 505 #define CONFIG_HAS_ETH1 506 #define CONFIG_HAS_ETH2 507 508 #define CONFIG_FSL_SGMII_RISER 1 509 #define SGMII_RISER_PHY_OFFSET 0x1b 510 511 #ifdef CONFIG_FSL_SGMII_RISER 512 #define CONFIG_SYS_TBIPA_VALUE 8 513 #endif 514 515 #endif 516 517 /* PCIe */ 518 #define CONFIG_PCI /* Enable PCI/PCIE */ 519 #define CONFIG_PCIE1 /* PCIE controller 1 */ 520 #define CONFIG_PCIE2 /* PCIE controller 2 */ 521 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 522 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 523 524 #define CONFIG_SYS_PCI_64BIT 525 526 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 527 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 528 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 529 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 530 531 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 532 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 533 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 534 535 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 536 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 537 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 538 539 #ifdef CONFIG_PCI 540 #define CONFIG_PCI_PNP 541 #define CONFIG_PCI_SCAN_SHOW 542 #define CONFIG_CMD_PCI 543 #endif 544 545 #define CONFIG_CMDLINE_TAG 546 #define CONFIG_CMDLINE_EDITING 547 548 #define CONFIG_ARMV7_NONSEC 549 #define CONFIG_ARMV7_VIRT 550 #define CONFIG_PEN_ADDR_BIG_ENDIAN 551 #define CONFIG_LAYERSCAPE_NS_ACCESS 552 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 553 #define CONFIG_TIMER_CLK_FREQ 12500000 554 555 #define CONFIG_HWCONFIG 556 #define HWCONFIG_BUFFER_SIZE 256 557 558 #define CONFIG_FSL_DEVICE_DISABLE 559 560 561 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 562 563 #ifdef CONFIG_LPUART 564 #define CONFIG_EXTRA_ENV_SETTINGS \ 565 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 566 "fdt_high=0xffffffff\0" \ 567 "initrd_high=0xffffffff\0" \ 568 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 569 #else 570 #define CONFIG_EXTRA_ENV_SETTINGS \ 571 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 572 "fdt_high=0xffffffff\0" \ 573 "initrd_high=0xffffffff\0" \ 574 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 575 #endif 576 577 /* 578 * Miscellaneous configurable options 579 */ 580 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 581 #define CONFIG_AUTO_COMPLETE 582 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 583 #define CONFIG_SYS_PBSIZE \ 584 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 585 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 586 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 587 588 #define CONFIG_SYS_MEMTEST_START 0x80000000 589 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 590 591 #define CONFIG_SYS_LOAD_ADDR 0x82000000 592 593 #define CONFIG_LS102XA_STREAM_ID 594 595 /* 596 * Stack sizes 597 * The stack sizes are set up in start.S using the settings below 598 */ 599 #define CONFIG_STACKSIZE (30 * 1024) 600 601 #define CONFIG_SYS_INIT_SP_OFFSET \ 602 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 603 #define CONFIG_SYS_INIT_SP_ADDR \ 604 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 605 606 #ifdef CONFIG_SPL_BUILD 607 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 608 #else 609 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 610 #endif 611 612 /* 613 * Environment 614 */ 615 #define CONFIG_ENV_OVERWRITE 616 617 #if defined(CONFIG_SD_BOOT) 618 #define CONFIG_ENV_OFFSET 0x100000 619 #define CONFIG_ENV_IS_IN_MMC 620 #define CONFIG_SYS_MMC_ENV_DEV 0 621 #define CONFIG_ENV_SIZE 0x2000 622 #elif defined(CONFIG_QSPI_BOOT) 623 #define CONFIG_ENV_IS_IN_SPI_FLASH 624 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 625 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 626 #define CONFIG_ENV_SECT_SIZE 0x10000 627 #elif defined(CONFIG_NAND_BOOT) 628 #define CONFIG_ENV_IS_IN_NAND 629 #define CONFIG_ENV_SIZE 0x2000 630 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 631 #else 632 #define CONFIG_ENV_IS_IN_FLASH 633 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 634 #define CONFIG_ENV_SIZE 0x2000 635 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 636 #endif 637 638 #define CONFIG_MISC_INIT_R 639 640 /* Hash command with SHA acceleration supported in hardware */ 641 #ifdef CONFIG_FSL_CAAM 642 #define CONFIG_CMD_HASH 643 #define CONFIG_SHA_HW_ACCEL 644 #endif 645 646 #include <asm/fsl_secure_boot.h> 647 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 648 649 #endif 650