1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x30001000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #ifdef CONFIG_SECURE_BOOT 67 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 68 /* 69 * HDR would be appended at end of image and copied to DDR along 70 * with U-Boot image. 71 */ 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 73 CONFIG_U_BOOT_HDR_SIZE) 74 #else 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 76 #endif 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 81 #define CONFIG_SPL_NAND_BOOT 82 #endif 83 84 #ifdef CONFIG_SPIFLASH 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 86 #define CONFIG_SPL_SPI_SUPPORT 87 #define CONFIG_SPL_SPI_FLASH_SUPPORT 88 #define CONFIG_SPL_SPI_FLASH_MINIMAL 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 93 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 94 #ifndef CONFIG_SPL_BUILD 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #endif 97 #define CONFIG_SPL_SPI_BOOT 98 #endif 99 100 #ifdef CONFIG_SDCARD 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 102 #define CONFIG_SPL_MMC_SUPPORT 103 #define CONFIG_SPL_MMC_MINIMAL 104 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 105 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 106 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 107 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 109 #ifndef CONFIG_SPL_BUILD 110 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 111 #endif 112 #define CONFIG_SPL_MMC_BOOT 113 #endif 114 115 #endif 116 117 /* High Level Configuration Options */ 118 #define CONFIG_BOOKE 119 #define CONFIG_E500MC /* BOOKE e500mc family */ 120 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 121 #define CONFIG_MP /* support multiple processors */ 122 123 /* support deep sleep */ 124 #define CONFIG_DEEP_SLEEP 125 #if defined(CONFIG_DEEP_SLEEP) 126 #define CONFIG_BOARD_EARLY_INIT_F 127 #define CONFIG_SILENT_CONSOLE 128 #endif 129 130 #ifndef CONFIG_SYS_TEXT_BASE 131 #define CONFIG_SYS_TEXT_BASE 0xeff40000 132 #endif 133 134 #ifndef CONFIG_RESET_VECTOR_ADDRESS 135 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 136 #endif 137 138 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 139 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 140 #define CONFIG_FSL_IFC /* Enable IFC Support */ 141 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 142 #define CONFIG_PCI /* Enable PCI/PCIE */ 143 #define CONFIG_PCI_INDIRECT_BRIDGE 144 #define CONFIG_PCIE1 /* PCIE controller 1 */ 145 #define CONFIG_PCIE2 /* PCIE controller 2 */ 146 #define CONFIG_PCIE3 /* PCIE controller 3 */ 147 #define CONFIG_PCIE4 /* PCIE controller 4 */ 148 149 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 150 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 151 152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 153 154 #define CONFIG_ENV_OVERWRITE 155 156 #ifndef CONFIG_SYS_NO_FLASH 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CONFIG_SYS_FLASH_CFI 159 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 160 #endif 161 162 #if defined(CONFIG_SPIFLASH) 163 #define CONFIG_SYS_EXTRA_ENV_RELOC 164 #define CONFIG_ENV_IS_IN_SPI_FLASH 165 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 166 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 167 #define CONFIG_ENV_SECT_SIZE 0x10000 168 #elif defined(CONFIG_SDCARD) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_MMC 171 #define CONFIG_SYS_MMC_ENV_DEV 0 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_OFFSET (512 * 0x800) 174 #elif defined(CONFIG_NAND) 175 #ifdef CONFIG_SECURE_BOOT 176 #define CONFIG_RAMBOOT_NAND 177 #define CONFIG_BOOTSCRIPT_COPY_RAM 178 #endif 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_ENV_IS_IN_NAND 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 183 #else 184 #define CONFIG_ENV_IS_IN_FLASH 185 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 188 #endif 189 190 #define CONFIG_SYS_CLK_FREQ 100000000 191 #define CONFIG_DDR_CLK_FREQ 66666666 192 193 /* 194 * These can be toggled for performance analysis, otherwise use default. 195 */ 196 #define CONFIG_SYS_CACHE_STASHING 197 #define CONFIG_BACKSIDE_L2_CACHE 198 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 199 #define CONFIG_BTB /* toggle branch predition */ 200 #define CONFIG_DDR_ECC 201 #ifdef CONFIG_DDR_ECC 202 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 203 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 204 #endif 205 206 #define CONFIG_ENABLE_36BIT_PHYS 207 208 #define CONFIG_ADDR_MAP 209 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 210 211 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 212 #define CONFIG_SYS_MEMTEST_END 0x00400000 213 #define CONFIG_SYS_ALT_MEMTEST 214 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 215 216 /* 217 * Config the L3 Cache as L3 SRAM 218 */ 219 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 220 /* 221 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 222 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 223 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 224 */ 225 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 226 #define CONFIG_SYS_L3_SIZE 256 << 10 227 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 228 #ifdef CONFIG_RAMBOOT_PBL 229 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 230 #endif 231 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 232 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 233 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 234 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 235 236 #define CONFIG_SYS_DCSRBAR 0xf0000000 237 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 238 239 /* 240 * DDR Setup 241 */ 242 #define CONFIG_VERY_BIG_RAM 243 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 244 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 245 246 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 247 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 248 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 249 250 #define CONFIG_DDR_SPD 251 #ifndef CONFIG_SYS_FSL_DDR4 252 #define CONFIG_SYS_FSL_DDR3 253 #endif 254 255 #define CONFIG_SYS_SPD_BUS_NUM 0 256 #define SPD_EEPROM_ADDRESS 0x51 257 258 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 259 260 /* 261 * IFC Definitions 262 */ 263 #define CONFIG_SYS_FLASH_BASE 0xe8000000 264 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 265 266 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 267 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 268 CSPR_PORT_SIZE_16 | \ 269 CSPR_MSEL_NOR | \ 270 CSPR_V) 271 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 272 273 /* 274 * TDM Definition 275 */ 276 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 277 278 /* NOR Flash Timing Params */ 279 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 280 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 281 FTIM0_NOR_TEADC(0x5) | \ 282 FTIM0_NOR_TEAHC(0x5)) 283 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 284 FTIM1_NOR_TRAD_NOR(0x1A) |\ 285 FTIM1_NOR_TSEQRAD_NOR(0x13)) 286 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 287 FTIM2_NOR_TCH(0x4) | \ 288 FTIM2_NOR_TWPH(0x0E) | \ 289 FTIM2_NOR_TWP(0x1c)) 290 #define CONFIG_SYS_NOR_FTIM3 0x0 291 292 #define CONFIG_SYS_FLASH_QUIET_TEST 293 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 294 295 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 296 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 297 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 298 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 299 300 #define CONFIG_SYS_FLASH_EMPTY_INFO 301 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 302 303 /* CPLD on IFC */ 304 #define CPLD_LBMAP_MASK 0x3F 305 #define CPLD_BANK_SEL_MASK 0x07 306 #define CPLD_BANK_OVERRIDE 0x40 307 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 308 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 309 #define CPLD_LBMAP_RESET 0xFF 310 #define CPLD_LBMAP_SHIFT 0x03 311 312 #if defined(CONFIG_T1042RDB_PI) 313 #define CPLD_DIU_SEL_DFP 0x80 314 #elif defined(CONFIG_T1042D4RDB) 315 #define CPLD_DIU_SEL_DFP 0xc0 316 #endif 317 318 #if defined(CONFIG_T1040D4RDB) 319 #define CPLD_INT_MASK_ALL 0xFF 320 #define CPLD_INT_MASK_THERM 0x80 321 #define CPLD_INT_MASK_DVI_DFP 0x40 322 #define CPLD_INT_MASK_QSGMII1 0x20 323 #define CPLD_INT_MASK_QSGMII2 0x10 324 #define CPLD_INT_MASK_SGMI1 0x08 325 #define CPLD_INT_MASK_SGMI2 0x04 326 #define CPLD_INT_MASK_TDMR1 0x02 327 #define CPLD_INT_MASK_TDMR2 0x01 328 #endif 329 330 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 331 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 332 #define CONFIG_SYS_CSPR2_EXT (0xf) 333 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 334 | CSPR_PORT_SIZE_8 \ 335 | CSPR_MSEL_GPCM \ 336 | CSPR_V) 337 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 338 #define CONFIG_SYS_CSOR2 0x0 339 /* CPLD Timing parameters for IFC CS2 */ 340 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 341 FTIM0_GPCM_TEADC(0x0e) | \ 342 FTIM0_GPCM_TEAHC(0x0e)) 343 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 344 FTIM1_GPCM_TRAD(0x1f)) 345 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 346 FTIM2_GPCM_TCH(0x8) | \ 347 FTIM2_GPCM_TWP(0x1f)) 348 #define CONFIG_SYS_CS2_FTIM3 0x0 349 350 /* NAND Flash on IFC */ 351 #define CONFIG_NAND_FSL_IFC 352 #define CONFIG_SYS_NAND_BASE 0xff800000 353 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 354 355 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 356 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 357 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 358 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 359 | CSPR_V) 360 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 361 362 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 363 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 364 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 365 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 366 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 367 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 368 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 369 370 #define CONFIG_SYS_NAND_ONFI_DETECTION 371 372 /* ONFI NAND Flash mode0 Timing Params */ 373 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 374 FTIM0_NAND_TWP(0x18) | \ 375 FTIM0_NAND_TWCHT(0x07) | \ 376 FTIM0_NAND_TWH(0x0a)) 377 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 378 FTIM1_NAND_TWBE(0x39) | \ 379 FTIM1_NAND_TRR(0x0e) | \ 380 FTIM1_NAND_TRP(0x18)) 381 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 382 FTIM2_NAND_TREH(0x0a) | \ 383 FTIM2_NAND_TWHRE(0x1e)) 384 #define CONFIG_SYS_NAND_FTIM3 0x0 385 386 #define CONFIG_SYS_NAND_DDR_LAW 11 387 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 388 #define CONFIG_SYS_MAX_NAND_DEVICE 1 389 #define CONFIG_CMD_NAND 390 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 392 393 #if defined(CONFIG_NAND) 394 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 395 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 403 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 404 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 405 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 406 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 407 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 408 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 409 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 410 #else 411 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 412 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 413 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 420 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 421 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 422 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 423 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 424 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 425 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 426 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 427 #endif 428 429 #ifdef CONFIG_SPL_BUILD 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 431 #else 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 433 #endif 434 435 #if defined(CONFIG_RAMBOOT_PBL) 436 #define CONFIG_SYS_RAMBOOT 437 #endif 438 439 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 440 #if defined(CONFIG_NAND) 441 #define CONFIG_A008044_WORKAROUND 442 #endif 443 #endif 444 445 #define CONFIG_BOARD_EARLY_INIT_R 446 #define CONFIG_MISC_INIT_R 447 448 #define CONFIG_HWCONFIG 449 450 /* define to use L1 as initial stack */ 451 #define CONFIG_L1_INIT_RAM 452 #define CONFIG_SYS_INIT_RAM_LOCK 453 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 456 /* The assembler doesn't like typecast */ 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 458 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 459 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 460 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 461 462 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 463 GENERATED_GBL_DATA_SIZE) 464 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 465 466 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 467 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 468 469 /* Serial Port - controlled on board with jumper J8 470 * open - index 2 471 * shorted - index 1 472 */ 473 #define CONFIG_CONS_INDEX 1 474 #define CONFIG_SYS_NS16550_SERIAL 475 #define CONFIG_SYS_NS16550_REG_SIZE 1 476 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 477 478 #define CONFIG_SYS_BAUDRATE_TABLE \ 479 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 480 481 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 482 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 483 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 484 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 485 #ifndef CONFIG_SPL_BUILD 486 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 487 #endif 488 489 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 490 /* Video */ 491 #define CONFIG_FSL_DIU_FB 492 493 #ifdef CONFIG_FSL_DIU_FB 494 #define CONFIG_FSL_DIU_CH7301 495 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 496 #define CONFIG_VIDEO 497 #define CONFIG_CMD_BMP 498 #define CONFIG_CFB_CONSOLE 499 #define CONFIG_CFB_CONSOLE_ANSI 500 #define CONFIG_VIDEO_SW_CURSOR 501 #define CONFIG_VGA_AS_SINGLE_DEVICE 502 #define CONFIG_VIDEO_LOGO 503 #define CONFIG_VIDEO_BMP_LOGO 504 #endif 505 #endif 506 507 /* I2C */ 508 #define CONFIG_SYS_I2C 509 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 510 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 511 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 512 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 519 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 520 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 521 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 522 523 /* I2C bus multiplexer */ 524 #define I2C_MUX_PCA_ADDR 0x70 525 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 526 #define I2C_MUX_CH_DEFAULT 0x8 527 #endif 528 529 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 530 /* LDI/DVI Encoder for display */ 531 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 532 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 533 534 /* 535 * RTC configuration 536 */ 537 #define RTC 538 #define CONFIG_RTC_DS1337 1 539 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 540 541 /*DVI encoder*/ 542 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 543 #endif 544 545 /* 546 * eSPI - Enhanced SPI 547 */ 548 #define CONFIG_SPI_FLASH_BAR 549 #define CONFIG_SF_DEFAULT_SPEED 10000000 550 #define CONFIG_SF_DEFAULT_MODE 0 551 #define CONFIG_ENV_SPI_BUS 0 552 #define CONFIG_ENV_SPI_CS 0 553 #define CONFIG_ENV_SPI_MAX_HZ 10000000 554 #define CONFIG_ENV_SPI_MODE 0 555 556 /* 557 * General PCI 558 * Memory space is mapped 1-1, but I/O space must start from 0. 559 */ 560 561 #ifdef CONFIG_PCI 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 563 #ifdef CONFIG_PCIE1 564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 571 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 572 #endif 573 574 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 575 #ifdef CONFIG_PCIE2 576 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 577 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 578 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 579 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 580 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 581 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 582 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 587 #ifdef CONFIG_PCIE3 588 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 589 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 590 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 591 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 592 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 593 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 594 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 595 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 4, Base address 203000 */ 599 #ifdef CONFIG_PCIE4 600 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 601 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 602 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 603 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 604 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 605 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 606 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 607 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 608 #endif 609 610 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 611 612 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 613 #define CONFIG_DOS_PARTITION 614 #endif /* CONFIG_PCI */ 615 616 /* SATA */ 617 #define CONFIG_FSL_SATA_V2 618 #ifdef CONFIG_FSL_SATA_V2 619 #define CONFIG_LIBATA 620 #define CONFIG_FSL_SATA 621 622 #define CONFIG_SYS_SATA_MAX_DEVICE 1 623 #define CONFIG_SATA1 624 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 625 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 626 627 #define CONFIG_LBA48 628 #define CONFIG_CMD_SATA 629 #define CONFIG_DOS_PARTITION 630 #endif 631 632 /* 633 * USB 634 */ 635 #define CONFIG_HAS_FSL_DR_USB 636 637 #ifdef CONFIG_HAS_FSL_DR_USB 638 #define CONFIG_USB_EHCI 639 640 #ifdef CONFIG_USB_EHCI 641 #define CONFIG_USB_EHCI_FSL 642 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 643 #endif 644 #endif 645 646 #define CONFIG_MMC 647 648 #ifdef CONFIG_MMC 649 #define CONFIG_FSL_ESDHC 650 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 651 #define CONFIG_GENERIC_MMC 652 #define CONFIG_DOS_PARTITION 653 #endif 654 655 /* Qman/Bman */ 656 #ifndef CONFIG_NOBQFMAN 657 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 658 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 659 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 660 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 661 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 662 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 663 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 664 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 665 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 666 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 667 CONFIG_SYS_BMAN_CENA_SIZE) 668 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 669 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 670 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 671 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 672 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 673 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 674 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 675 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 676 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 677 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 678 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 679 CONFIG_SYS_QMAN_CENA_SIZE) 680 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 681 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 682 683 #define CONFIG_SYS_DPAA_FMAN 684 #define CONFIG_SYS_DPAA_PME 685 686 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 687 #define CONFIG_QE 688 #define CONFIG_U_QE 689 #endif 690 691 /* Default address of microcode for the Linux Fman driver */ 692 #if defined(CONFIG_SPIFLASH) 693 /* 694 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 695 * env, so we got 0x110000. 696 */ 697 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 698 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 699 #elif defined(CONFIG_SDCARD) 700 /* 701 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 702 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 703 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 704 */ 705 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 706 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 707 #elif defined(CONFIG_NAND) 708 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 709 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 710 #else 711 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 712 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 713 #endif 714 715 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 716 #if defined(CONFIG_SPIFLASH) 717 #define CONFIG_SYS_QE_FW_ADDR 0x130000 718 #elif defined(CONFIG_SDCARD) 719 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 720 #elif defined(CONFIG_NAND) 721 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 722 #else 723 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 724 #endif 725 #endif 726 727 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 728 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 729 #endif /* CONFIG_NOBQFMAN */ 730 731 #ifdef CONFIG_SYS_DPAA_FMAN 732 #define CONFIG_FMAN_ENET 733 #define CONFIG_PHY_VITESSE 734 #define CONFIG_PHY_REALTEK 735 #endif 736 737 #ifdef CONFIG_FMAN_ENET 738 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 739 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 740 #elif defined(CONFIG_T1040D4RDB) 741 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 742 #elif defined(CONFIG_T1042D4RDB) 743 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 744 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 745 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 746 #endif 747 748 #ifdef CONFIG_T104XD4RDB 749 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 750 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 751 #else 752 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 753 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 754 #endif 755 756 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 757 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 758 #define CONFIG_VSC9953 759 #define CONFIG_CMD_ETHSW 760 #ifdef CONFIG_T1040RDB 761 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 762 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 763 #else 764 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 765 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 766 #endif 767 #endif 768 769 #define CONFIG_MII /* MII PHY management */ 770 #define CONFIG_ETHPRIME "FM1@DTSEC4" 771 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 772 #endif 773 774 /* 775 * Environment 776 */ 777 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 778 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 779 780 /* 781 * Command line configuration. 782 */ 783 #ifdef CONFIG_T1042RDB_PI 784 #define CONFIG_CMD_DATE 785 #endif 786 #define CONFIG_CMD_ERRATA 787 #define CONFIG_CMD_IRQ 788 #define CONFIG_CMD_REGINFO 789 790 #ifdef CONFIG_PCI 791 #define CONFIG_CMD_PCI 792 #endif 793 794 /* Hash command with SHA acceleration supported in hardware */ 795 #ifdef CONFIG_FSL_CAAM 796 #define CONFIG_CMD_HASH 797 #define CONFIG_SHA_HW_ACCEL 798 #endif 799 800 /* 801 * Miscellaneous configurable options 802 */ 803 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 804 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 805 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 806 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 807 #ifdef CONFIG_CMD_KGDB 808 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 809 #else 810 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 811 #endif 812 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 813 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 814 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 815 816 /* 817 * For booting Linux, the board info and command line data 818 * have to be in the first 64 MB of memory, since this is 819 * the maximum mapped by the Linux kernel during initialization. 820 */ 821 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 822 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 823 824 #ifdef CONFIG_CMD_KGDB 825 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 826 #endif 827 828 /* 829 * Dynamic MTD Partition support with mtdparts 830 */ 831 #ifndef CONFIG_SYS_NO_FLASH 832 #define CONFIG_MTD_DEVICE 833 #define CONFIG_MTD_PARTITIONS 834 #define CONFIG_CMD_MTDPARTS 835 #define CONFIG_FLASH_CFI_MTD 836 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 837 "spi0=spife110000.0" 838 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 839 "128k(dtb),96m(fs),-(user);"\ 840 "fff800000.flash:2m(uboot),9m(kernel),"\ 841 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 842 "2m(uboot),9m(kernel),128k(dtb),-(user)" 843 #endif 844 845 /* 846 * Environment Configuration 847 */ 848 #define CONFIG_ROOTPATH "/opt/nfsroot" 849 #define CONFIG_BOOTFILE "uImage" 850 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 851 852 /* default location for tftp and bootm */ 853 #define CONFIG_LOADADDR 1000000 854 855 856 #define CONFIG_BAUDRATE 115200 857 858 #define __USB_PHY_TYPE utmi 859 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 860 861 #ifdef CONFIG_T1040RDB 862 #define FDTFILE "t1040rdb/t1040rdb.dtb" 863 #elif defined(CONFIG_T1042RDB_PI) 864 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 865 #elif defined(CONFIG_T1042RDB) 866 #define FDTFILE "t1042rdb/t1042rdb.dtb" 867 #elif defined(CONFIG_T1040D4RDB) 868 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 869 #elif defined(CONFIG_T1042D4RDB) 870 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 871 #endif 872 873 #ifdef CONFIG_FSL_DIU_FB 874 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 875 #else 876 #define DIU_ENVIRONMENT 877 #endif 878 879 #define CONFIG_EXTRA_ENV_SETTINGS \ 880 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 881 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 882 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 883 "netdev=eth0\0" \ 884 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 885 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 886 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 887 "tftpflash=tftpboot $loadaddr $uboot && " \ 888 "protect off $ubootaddr +$filesize && " \ 889 "erase $ubootaddr +$filesize && " \ 890 "cp.b $loadaddr $ubootaddr $filesize && " \ 891 "protect on $ubootaddr +$filesize && " \ 892 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 893 "consoledev=ttyS0\0" \ 894 "ramdiskaddr=2000000\0" \ 895 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 896 "fdtaddr=1e00000\0" \ 897 "fdtfile=" __stringify(FDTFILE) "\0" \ 898 "bdev=sda3\0" 899 900 #define CONFIG_LINUX \ 901 "setenv bootargs root=/dev/ram rw " \ 902 "console=$consoledev,$baudrate $othbootargs;" \ 903 "setenv ramdiskaddr 0x02000000;" \ 904 "setenv fdtaddr 0x00c00000;" \ 905 "setenv loadaddr 0x1000000;" \ 906 "bootm $loadaddr $ramdiskaddr $fdtaddr" 907 908 #define CONFIG_HDBOOT \ 909 "setenv bootargs root=/dev/$bdev rw " \ 910 "console=$consoledev,$baudrate $othbootargs;" \ 911 "tftp $loadaddr $bootfile;" \ 912 "tftp $fdtaddr $fdtfile;" \ 913 "bootm $loadaddr - $fdtaddr" 914 915 #define CONFIG_NFSBOOTCOMMAND \ 916 "setenv bootargs root=/dev/nfs rw " \ 917 "nfsroot=$serverip:$rootpath " \ 918 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 919 "console=$consoledev,$baudrate $othbootargs;" \ 920 "tftp $loadaddr $bootfile;" \ 921 "tftp $fdtaddr $fdtfile;" \ 922 "bootm $loadaddr - $fdtaddr" 923 924 #define CONFIG_RAMBOOTCOMMAND \ 925 "setenv bootargs root=/dev/ram rw " \ 926 "console=$consoledev,$baudrate $othbootargs;" \ 927 "tftp $ramdiskaddr $ramdiskfile;" \ 928 "tftp $loadaddr $bootfile;" \ 929 "tftp $fdtaddr $fdtfile;" \ 930 "bootm $loadaddr $ramdiskaddr $fdtaddr" 931 932 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 933 934 #include <asm/fsl_secure_boot.h> 935 936 #endif /* __CONFIG_H */ 937