1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SPL_LIBGENERIC_SUPPORT 71 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 72 #define CONFIG_SPL_WATCHDOG_SUPPORT 73 #define CONFIG_SPL_SERIAL_SUPPORT 74 #define CONFIG_SPL_MMC_SUPPORT 75 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 76 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 77 78 #define CONFIG_SPL_TEXT_BASE 0x10000000 79 #define CONFIG_SPL_MAX_SIZE 0x1a000 80 #define CONFIG_SPL_STACK 0x1001d000 81 #define CONFIG_SPL_PAD_TO 0x1c000 82 #define CONFIG_SYS_TEXT_BASE 0x82000000 83 84 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 85 CONFIG_SYS_MONITOR_LEN) 86 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 87 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 88 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 89 #define CONFIG_SYS_MONITOR_LEN 0xc0000 90 #endif 91 92 #ifdef CONFIG_QSPI_BOOT 93 #define CONFIG_SYS_TEXT_BASE 0x40010000 94 #endif 95 96 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 97 #define CONFIG_SYS_NO_FLASH 98 #endif 99 100 #ifdef CONFIG_NAND_BOOT 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 102 #define CONFIG_SPL_FRAMEWORK 103 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 104 #define CONFIG_SPL_LIBGENERIC_SUPPORT 105 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 106 #define CONFIG_SPL_WATCHDOG_SUPPORT 107 #define CONFIG_SPL_SERIAL_SUPPORT 108 #define CONFIG_SPL_NAND_SUPPORT 109 110 #define CONFIG_SPL_TEXT_BASE 0x10000000 111 #define CONFIG_SPL_MAX_SIZE 0x1a000 112 #define CONFIG_SPL_STACK 0x1001d000 113 #define CONFIG_SPL_PAD_TO 0x1c000 114 #define CONFIG_SYS_TEXT_BASE 0x82000000 115 116 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 117 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 118 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 119 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 121 122 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 123 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 124 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 125 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 126 #define CONFIG_SYS_MONITOR_LEN 0x80000 127 #endif 128 129 #ifndef CONFIG_SYS_TEXT_BASE 130 #define CONFIG_SYS_TEXT_BASE 0x60100000 131 #endif 132 133 #define CONFIG_NR_DRAM_BANKS 1 134 135 #define CONFIG_DDR_SPD 136 #define SPD_EEPROM_ADDRESS 0x51 137 #define CONFIG_SYS_SPD_BUS_NUM 0 138 139 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 140 #ifndef CONFIG_SYS_FSL_DDR4 141 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 142 #define CONFIG_SYS_DDR_RAW_TIMING 143 #endif 144 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 145 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 146 147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150 #define CONFIG_DDR_ECC 151 #ifdef CONFIG_DDR_ECC 152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 153 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 154 #endif 155 156 #define CONFIG_SYS_HAS_SERDES 157 158 #define CONFIG_FSL_CAAM /* Enable CAAM */ 159 160 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 161 !defined(CONFIG_QSPI_BOOT) 162 #define CONFIG_U_QE 163 #endif 164 165 /* 166 * IFC Definitions 167 */ 168 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 169 #define CONFIG_FSL_IFC 170 #define CONFIG_SYS_FLASH_BASE 0x60000000 171 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 172 173 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 174 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 175 CSPR_PORT_SIZE_16 | \ 176 CSPR_MSEL_NOR | \ 177 CSPR_V) 178 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 179 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 180 + 0x8000000) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 185 186 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 187 CSOR_NOR_TRHZ_80) 188 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 189 FTIM0_NOR_TEADC(0x5) | \ 190 FTIM0_NOR_TEAHC(0x5)) 191 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 192 FTIM1_NOR_TRAD_NOR(0x1a) | \ 193 FTIM1_NOR_TSEQRAD_NOR(0x13)) 194 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 195 FTIM2_NOR_TCH(0x4) | \ 196 FTIM2_NOR_TWPH(0xe) | \ 197 FTIM2_NOR_TWP(0x1c)) 198 #define CONFIG_SYS_NOR_FTIM3 0 199 200 #define CONFIG_FLASH_CFI_DRIVER 201 #define CONFIG_SYS_FLASH_CFI 202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 203 #define CONFIG_SYS_FLASH_QUIET_TEST 204 #define CONFIG_FLASH_SHOW_PROGRESS 45 205 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 206 #define CONFIG_SYS_WRITE_SWAPPED_DATA 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 215 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 216 217 /* 218 * NAND Flash Definitions 219 */ 220 #define CONFIG_NAND_FSL_IFC 221 222 #define CONFIG_SYS_NAND_BASE 0x7e800000 223 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 224 225 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 226 227 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 228 | CSPR_PORT_SIZE_8 \ 229 | CSPR_MSEL_NAND \ 230 | CSPR_V) 231 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 232 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 233 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 234 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 235 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 236 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 237 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 238 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 239 240 #define CONFIG_SYS_NAND_ONFI_DETECTION 241 242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 243 FTIM0_NAND_TWP(0x18) | \ 244 FTIM0_NAND_TWCHT(0x7) | \ 245 FTIM0_NAND_TWH(0xa)) 246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 247 FTIM1_NAND_TWBE(0x39) | \ 248 FTIM1_NAND_TRR(0xe) | \ 249 FTIM1_NAND_TRP(0x18)) 250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 251 FTIM2_NAND_TREH(0xa) | \ 252 FTIM2_NAND_TWHRE(0x1e)) 253 #define CONFIG_SYS_NAND_FTIM3 0x0 254 255 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_CMD_NAND 258 259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 260 #endif 261 262 /* 263 * QIXIS Definitions 264 */ 265 #define CONFIG_FSL_QIXIS 266 267 #ifdef CONFIG_FSL_QIXIS 268 #define QIXIS_BASE 0x7fb00000 269 #define QIXIS_BASE_PHYS QIXIS_BASE 270 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 271 #define QIXIS_LBMAP_SWITCH 6 272 #define QIXIS_LBMAP_MASK 0x0f 273 #define QIXIS_LBMAP_SHIFT 0 274 #define QIXIS_LBMAP_DFLTBANK 0x00 275 #define QIXIS_LBMAP_ALTBANK 0x04 276 #define QIXIS_PWR_CTL 0x21 277 #define QIXIS_PWR_CTL_POWEROFF 0x80 278 #define QIXIS_RST_CTL_RESET 0x44 279 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 280 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 281 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 282 283 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 284 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 285 CSPR_PORT_SIZE_8 | \ 286 CSPR_MSEL_GPCM | \ 287 CSPR_V) 288 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 289 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 290 CSOR_NOR_NOR_MODE_AVD_NOR | \ 291 CSOR_NOR_TRHZ_80) 292 293 /* 294 * QIXIS Timing parameters for IFC GPCM 295 */ 296 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 297 FTIM0_GPCM_TEADC(0xe) | \ 298 FTIM0_GPCM_TEAHC(0xe)) 299 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 300 FTIM1_GPCM_TRAD(0x1f)) 301 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 302 FTIM2_GPCM_TCH(0xe) | \ 303 FTIM2_GPCM_TWP(0xf0)) 304 #define CONFIG_SYS_FPGA_FTIM3 0x0 305 #endif 306 307 #if defined(CONFIG_NAND_BOOT) 308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 332 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 333 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 334 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 335 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 336 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 337 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 338 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 339 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 340 #else 341 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 342 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 343 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 344 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 345 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 346 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 347 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 348 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 349 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 365 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 366 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 367 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 368 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 369 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 370 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 371 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 372 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 373 #endif 374 375 /* 376 * Serial Port 377 */ 378 #ifdef CONFIG_LPUART 379 #define CONFIG_LPUART_32B_REG 380 #else 381 #define CONFIG_CONS_INDEX 1 382 #define CONFIG_SYS_NS16550_SERIAL 383 #ifndef CONFIG_DM_SERIAL 384 #define CONFIG_SYS_NS16550_REG_SIZE 1 385 #endif 386 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 387 #endif 388 389 #define CONFIG_BAUDRATE 115200 390 391 /* 392 * I2C 393 */ 394 #define CONFIG_SYS_I2C 395 #define CONFIG_SYS_I2C_MXC 396 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 397 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 398 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 399 400 /* 401 * I2C bus multiplexer 402 */ 403 #define I2C_MUX_PCA_ADDR_PRI 0x77 404 #define I2C_MUX_CH_DEFAULT 0x8 405 #define I2C_MUX_CH_CH7301 0xC 406 407 /* 408 * MMC 409 */ 410 #define CONFIG_MMC 411 #define CONFIG_FSL_ESDHC 412 #define CONFIG_GENERIC_MMC 413 414 #define CONFIG_DOS_PARTITION 415 416 /* SPI */ 417 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 418 /* QSPI */ 419 #define QSPI0_AMBA_BASE 0x40000000 420 #define FSL_QSPI_FLASH_SIZE (1 << 24) 421 #define FSL_QSPI_FLASH_NUM 2 422 423 /* DSPI */ 424 425 /* DM SPI */ 426 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 427 #define CONFIG_DM_SPI_FLASH 428 #define CONFIG_SPI_FLASH_DATAFLASH 429 #endif 430 #endif 431 432 /* 433 * USB 434 */ 435 /* EHCI Support - disbaled by default */ 436 /*#define CONFIG_HAS_FSL_DR_USB*/ 437 438 #ifdef CONFIG_HAS_FSL_DR_USB 439 #define CONFIG_USB_EHCI 440 #define CONFIG_USB_EHCI_FSL 441 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 442 #endif 443 444 /*XHCI Support - enabled by default*/ 445 #define CONFIG_HAS_FSL_XHCI_USB 446 447 #ifdef CONFIG_HAS_FSL_XHCI_USB 448 #define CONFIG_USB_XHCI_FSL 449 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 450 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 451 #endif 452 453 /* 454 * Video 455 */ 456 #define CONFIG_FSL_DCU_FB 457 458 #ifdef CONFIG_FSL_DCU_FB 459 #define CONFIG_VIDEO 460 #define CONFIG_CMD_BMP 461 #define CONFIG_CFB_CONSOLE 462 #define CONFIG_VGA_AS_SINGLE_DEVICE 463 #define CONFIG_VIDEO_LOGO 464 #define CONFIG_VIDEO_BMP_LOGO 465 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 466 467 #define CONFIG_FSL_DIU_CH7301 468 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 469 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 470 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 471 #endif 472 473 /* 474 * eTSEC 475 */ 476 #define CONFIG_TSEC_ENET 477 478 #ifdef CONFIG_TSEC_ENET 479 #define CONFIG_MII 480 #define CONFIG_MII_DEFAULT_TSEC 3 481 #define CONFIG_TSEC1 1 482 #define CONFIG_TSEC1_NAME "eTSEC1" 483 #define CONFIG_TSEC2 1 484 #define CONFIG_TSEC2_NAME "eTSEC2" 485 #define CONFIG_TSEC3 1 486 #define CONFIG_TSEC3_NAME "eTSEC3" 487 488 #define TSEC1_PHY_ADDR 1 489 #define TSEC2_PHY_ADDR 2 490 #define TSEC3_PHY_ADDR 3 491 492 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 493 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 494 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 495 496 #define TSEC1_PHYIDX 0 497 #define TSEC2_PHYIDX 0 498 #define TSEC3_PHYIDX 0 499 500 #define CONFIG_ETHPRIME "eTSEC1" 501 502 #define CONFIG_PHY_GIGE 503 #define CONFIG_PHYLIB 504 #define CONFIG_PHY_REALTEK 505 506 #define CONFIG_HAS_ETH0 507 #define CONFIG_HAS_ETH1 508 #define CONFIG_HAS_ETH2 509 510 #define CONFIG_FSL_SGMII_RISER 1 511 #define SGMII_RISER_PHY_OFFSET 0x1b 512 513 #ifdef CONFIG_FSL_SGMII_RISER 514 #define CONFIG_SYS_TBIPA_VALUE 8 515 #endif 516 517 #endif 518 519 /* PCIe */ 520 #define CONFIG_PCI /* Enable PCI/PCIE */ 521 #define CONFIG_PCIE1 /* PCIE controller 1 */ 522 #define CONFIG_PCIE2 /* PCIE controller 2 */ 523 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 524 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 525 526 #define CONFIG_SYS_PCI_64BIT 527 528 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 529 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 530 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 531 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 532 533 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 534 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 535 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 536 537 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 538 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 539 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 540 541 #ifdef CONFIG_PCI 542 #define CONFIG_PCI_PNP 543 #define CONFIG_PCI_SCAN_SHOW 544 #define CONFIG_CMD_PCI 545 #endif 546 547 #define CONFIG_CMDLINE_TAG 548 #define CONFIG_CMDLINE_EDITING 549 550 #define CONFIG_ARMV7_NONSEC 551 #define CONFIG_ARMV7_VIRT 552 #define CONFIG_PEN_ADDR_BIG_ENDIAN 553 #define CONFIG_LAYERSCAPE_NS_ACCESS 554 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 555 #define CONFIG_TIMER_CLK_FREQ 12500000 556 557 #define CONFIG_HWCONFIG 558 #define HWCONFIG_BUFFER_SIZE 256 559 560 #define CONFIG_FSL_DEVICE_DISABLE 561 562 563 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 564 565 #ifdef CONFIG_LPUART 566 #define CONFIG_EXTRA_ENV_SETTINGS \ 567 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 568 "fdt_high=0xffffffff\0" \ 569 "initrd_high=0xffffffff\0" \ 570 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 571 #else 572 #define CONFIG_EXTRA_ENV_SETTINGS \ 573 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 574 "fdt_high=0xffffffff\0" \ 575 "initrd_high=0xffffffff\0" \ 576 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 577 #endif 578 579 /* 580 * Miscellaneous configurable options 581 */ 582 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 583 #define CONFIG_AUTO_COMPLETE 584 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 585 #define CONFIG_SYS_PBSIZE \ 586 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 587 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 588 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 589 590 #define CONFIG_SYS_MEMTEST_START 0x80000000 591 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 592 593 #define CONFIG_SYS_LOAD_ADDR 0x82000000 594 595 #define CONFIG_LS102XA_STREAM_ID 596 597 /* 598 * Stack sizes 599 * The stack sizes are set up in start.S using the settings below 600 */ 601 #define CONFIG_STACKSIZE (30 * 1024) 602 603 #define CONFIG_SYS_INIT_SP_OFFSET \ 604 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 605 #define CONFIG_SYS_INIT_SP_ADDR \ 606 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 607 608 #ifdef CONFIG_SPL_BUILD 609 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 610 #else 611 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 612 #endif 613 614 /* 615 * Environment 616 */ 617 #define CONFIG_ENV_OVERWRITE 618 619 #if defined(CONFIG_SD_BOOT) 620 #define CONFIG_ENV_OFFSET 0x100000 621 #define CONFIG_ENV_IS_IN_MMC 622 #define CONFIG_SYS_MMC_ENV_DEV 0 623 #define CONFIG_ENV_SIZE 0x2000 624 #elif defined(CONFIG_QSPI_BOOT) 625 #define CONFIG_ENV_IS_IN_SPI_FLASH 626 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 627 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 628 #define CONFIG_ENV_SECT_SIZE 0x10000 629 #elif defined(CONFIG_NAND_BOOT) 630 #define CONFIG_ENV_IS_IN_NAND 631 #define CONFIG_ENV_SIZE 0x2000 632 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 633 #else 634 #define CONFIG_ENV_IS_IN_FLASH 635 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 636 #define CONFIG_ENV_SIZE 0x2000 637 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 638 #endif 639 640 #define CONFIG_MISC_INIT_R 641 642 /* Hash command with SHA acceleration supported in hardware */ 643 #ifdef CONFIG_FSL_CAAM 644 #define CONFIG_CMD_HASH 645 #define CONFIG_SHA_HW_ACCEL 646 #endif 647 648 #include <asm/fsl_secure_boot.h> 649 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 650 651 #endif 652