1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 #define CONFIG_DEEP_SLEEP 24 #ifdef CONFIG_DEEP_SLEEP 25 #define CONFIG_SILENT_CONSOLE 26 #endif 27 28 /* 29 * Size of malloc() pool 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 32 33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 35 36 /* 37 * USB 38 */ 39 40 /* 41 * EHCI Support - disbaled by default as 42 * there is no signal coming out of soc on 43 * this board for this controller. However, 44 * the silicon still has this controller, 45 * and anyone can use this controller by 46 * taking signals out on their board. 47 */ 48 49 /*#define CONFIG_HAS_FSL_DR_USB*/ 50 51 #ifdef CONFIG_HAS_FSL_DR_USB 52 #define CONFIG_USB_EHCI 53 #define CONFIG_USB_EHCI_FSL 54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 55 #endif 56 57 /* XHCI Support - enabled by default */ 58 #define CONFIG_HAS_FSL_XHCI_USB 59 60 #ifdef CONFIG_HAS_FSL_XHCI_USB 61 #define CONFIG_USB_XHCI_FSL 62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 64 #endif 65 66 /* 67 * Generic Timer Definitions 68 */ 69 #define GENERIC_TIMER_CLK 12500000 70 71 #define CONFIG_SYS_CLK_FREQ 100000000 72 #define CONFIG_DDR_CLK_FREQ 100000000 73 74 #define DDR_SDRAM_CFG 0x470c0008 75 #define DDR_CS0_BNDS 0x008000bf 76 #define DDR_CS0_CONFIG 0x80014302 77 #define DDR_TIMING_CFG_0 0x50550004 78 #define DDR_TIMING_CFG_1 0xbcb38c56 79 #define DDR_TIMING_CFG_2 0x0040d120 80 #define DDR_TIMING_CFG_3 0x010e1000 81 #define DDR_TIMING_CFG_4 0x00000001 82 #define DDR_TIMING_CFG_5 0x03401400 83 #define DDR_SDRAM_CFG_2 0x00401010 84 #define DDR_SDRAM_MODE 0x00061c60 85 #define DDR_SDRAM_MODE_2 0x00180000 86 #define DDR_SDRAM_INTERVAL 0x18600618 87 #define DDR_DDR_WRLVL_CNTL 0x8655f605 88 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 89 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 90 #define DDR_DDR_CDR1 0x80040000 91 #define DDR_DDR_CDR2 0x00000001 92 #define DDR_SDRAM_CLK_CNTL 0x02000000 93 #define DDR_DDR_ZQ_CNTL 0x89080600 94 #define DDR_CS0_CONFIG_2 0 95 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 96 #define SDRAM_CFG2_D_INIT 0x00000010 97 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 98 #define SDRAM_CFG2_FRC_SR 0x80000000 99 #define SDRAM_CFG_BI 0x00000001 100 101 #ifdef CONFIG_RAMBOOT_PBL 102 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 103 #endif 104 105 #ifdef CONFIG_SD_BOOT 106 #ifdef CONFIG_SD_BOOT_QSPI 107 #define CONFIG_SYS_FSL_PBL_RCW \ 108 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 109 #else 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 112 #endif 113 #define CONFIG_SPL_FRAMEWORK 114 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 115 #define CONFIG_SPL_WATCHDOG_SUPPORT 116 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 117 118 #ifdef CONFIG_SECURE_BOOT 119 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 120 /* 121 * HDR would be appended at end of image and copied to DDR along 122 * with U-Boot image. 123 */ 124 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 125 (CONFIG_U_BOOT_HDR_SIZE / 512) 126 #else 127 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 128 #endif /* ifdef CONFIG_SECURE_BOOT */ 129 130 #define CONFIG_SPL_TEXT_BASE 0x10000000 131 #define CONFIG_SPL_MAX_SIZE 0x1a000 132 #define CONFIG_SPL_STACK 0x1001d000 133 #define CONFIG_SPL_PAD_TO 0x1c000 134 #define CONFIG_SYS_TEXT_BASE 0x82000000 135 136 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 137 CONFIG_SYS_MONITOR_LEN) 138 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 139 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 140 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 141 142 #ifdef CONFIG_U_BOOT_HDR_SIZE 143 /* 144 * HDR would be appended at end of image and copied to DDR along 145 * with U-Boot image. Here u-boot max. size is 512K. So if binary 146 * size increases then increase this size in case of secure boot as 147 * it uses raw u-boot image instead of fit image. 148 */ 149 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 150 #else 151 #define CONFIG_SYS_MONITOR_LEN 0x80000 152 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 153 #endif 154 155 #ifdef CONFIG_QSPI_BOOT 156 #define CONFIG_SYS_TEXT_BASE 0x40010000 157 #endif 158 159 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 160 #define CONFIG_SYS_NO_FLASH 161 #endif 162 163 #ifndef CONFIG_SYS_TEXT_BASE 164 #define CONFIG_SYS_TEXT_BASE 0x60100000 165 #endif 166 167 #define CONFIG_NR_DRAM_BANKS 1 168 #define PHYS_SDRAM 0x80000000 169 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 170 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 #define CONFIG_SYS_HAS_SERDES 175 176 #define CONFIG_FSL_CAAM /* Enable CAAM */ 177 178 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 179 !defined(CONFIG_QSPI_BOOT) 180 #define CONFIG_U_QE 181 #endif 182 183 /* 184 * IFC Definitions 185 */ 186 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 187 #define CONFIG_FSL_IFC 188 #define CONFIG_SYS_FLASH_BASE 0x60000000 189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 190 191 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 192 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 193 CSPR_PORT_SIZE_16 | \ 194 CSPR_MSEL_NOR | \ 195 CSPR_V) 196 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 197 198 /* NOR Flash Timing Params */ 199 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 200 CSOR_NOR_TRHZ_80) 201 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 202 FTIM0_NOR_TEADC(0x5) | \ 203 FTIM0_NOR_TAVDS(0x0) | \ 204 FTIM0_NOR_TEAHC(0x5)) 205 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 206 FTIM1_NOR_TRAD_NOR(0x1A) | \ 207 FTIM1_NOR_TSEQRAD_NOR(0x13)) 208 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 209 FTIM2_NOR_TCH(0x4) | \ 210 FTIM2_NOR_TWP(0x1c) | \ 211 FTIM2_NOR_TWPH(0x0e)) 212 #define CONFIG_SYS_NOR_FTIM3 0 213 214 #define CONFIG_FLASH_CFI_DRIVER 215 #define CONFIG_SYS_FLASH_CFI 216 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 217 #define CONFIG_SYS_FLASH_QUIET_TEST 218 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 227 228 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 229 #define CONFIG_SYS_WRITE_SWAPPED_DATA 230 #endif 231 232 /* CPLD */ 233 234 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 235 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 236 237 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 238 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 239 CSPR_PORT_SIZE_8 | \ 240 CSPR_MSEL_GPCM | \ 241 CSPR_V) 242 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 243 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 244 CSOR_NOR_NOR_MODE_AVD_NOR | \ 245 CSOR_NOR_TRHZ_80) 246 247 /* CPLD Timing parameters for IFC GPCM */ 248 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 249 FTIM0_GPCM_TEADC(0xf) | \ 250 FTIM0_GPCM_TEAHC(0xf)) 251 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 252 FTIM1_GPCM_TRAD(0x3f)) 253 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 254 FTIM2_GPCM_TCH(0xf) | \ 255 FTIM2_GPCM_TWP(0xff)) 256 #define CONFIG_SYS_FPGA_FTIM3 0x0 257 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 258 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 259 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 260 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 261 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 262 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 263 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 264 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 265 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 266 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 267 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 268 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 269 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 270 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 271 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 272 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 273 274 /* 275 * Serial Port 276 */ 277 #ifdef CONFIG_LPUART 278 #define CONFIG_LPUART_32B_REG 279 #else 280 #define CONFIG_CONS_INDEX 1 281 #define CONFIG_SYS_NS16550_SERIAL 282 #ifndef CONFIG_DM_SERIAL 283 #define CONFIG_SYS_NS16550_REG_SIZE 1 284 #endif 285 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 286 #endif 287 288 #define CONFIG_BAUDRATE 115200 289 290 /* 291 * I2C 292 */ 293 #define CONFIG_SYS_I2C 294 #define CONFIG_SYS_I2C_MXC 295 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 296 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 297 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 298 299 /* EEPROM */ 300 #define CONFIG_ID_EEPROM 301 #define CONFIG_SYS_I2C_EEPROM_NXID 302 #define CONFIG_SYS_EEPROM_BUS_NUM 1 303 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 304 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 306 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 307 308 /* 309 * MMC 310 */ 311 #define CONFIG_MMC 312 #define CONFIG_FSL_ESDHC 313 #define CONFIG_GENERIC_MMC 314 315 #define CONFIG_DOS_PARTITION 316 317 /* SPI */ 318 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 319 /* QSPI */ 320 #define QSPI0_AMBA_BASE 0x40000000 321 #define FSL_QSPI_FLASH_SIZE (1 << 24) 322 #define FSL_QSPI_FLASH_NUM 2 323 324 /* DSPI */ 325 #endif 326 327 /* DM SPI */ 328 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 329 #define CONFIG_DM_SPI_FLASH 330 #endif 331 332 /* 333 * Video 334 */ 335 #define CONFIG_FSL_DCU_FB 336 337 #ifdef CONFIG_FSL_DCU_FB 338 #define CONFIG_VIDEO 339 #define CONFIG_CMD_BMP 340 #define CONFIG_CFB_CONSOLE 341 #define CONFIG_VGA_AS_SINGLE_DEVICE 342 #define CONFIG_VIDEO_LOGO 343 #define CONFIG_VIDEO_BMP_LOGO 344 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 345 346 #define CONFIG_FSL_DCU_SII9022A 347 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 348 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 349 #endif 350 351 /* 352 * eTSEC 353 */ 354 #define CONFIG_TSEC_ENET 355 356 #ifdef CONFIG_TSEC_ENET 357 #define CONFIG_MII 358 #define CONFIG_MII_DEFAULT_TSEC 1 359 #define CONFIG_TSEC1 1 360 #define CONFIG_TSEC1_NAME "eTSEC1" 361 #define CONFIG_TSEC2 1 362 #define CONFIG_TSEC2_NAME "eTSEC2" 363 #define CONFIG_TSEC3 1 364 #define CONFIG_TSEC3_NAME "eTSEC3" 365 366 #define TSEC1_PHY_ADDR 2 367 #define TSEC2_PHY_ADDR 0 368 #define TSEC3_PHY_ADDR 1 369 370 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 371 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 372 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 373 374 #define TSEC1_PHYIDX 0 375 #define TSEC2_PHYIDX 0 376 #define TSEC3_PHYIDX 0 377 378 #define CONFIG_ETHPRIME "eTSEC1" 379 380 #define CONFIG_PHY_GIGE 381 #define CONFIG_PHYLIB 382 #define CONFIG_PHY_ATHEROS 383 384 #define CONFIG_HAS_ETH0 385 #define CONFIG_HAS_ETH1 386 #define CONFIG_HAS_ETH2 387 #endif 388 389 /* PCIe */ 390 #define CONFIG_PCI /* Enable PCI/PCIE */ 391 #define CONFIG_PCIE1 /* PCIE controller 1 */ 392 #define CONFIG_PCIE2 /* PCIE controller 2 */ 393 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 394 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 395 396 #define CONFIG_SYS_PCI_64BIT 397 398 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 399 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 400 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 401 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 402 403 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 404 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 405 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 406 407 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 408 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 409 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 410 411 #ifdef CONFIG_PCI 412 #define CONFIG_PCI_PNP 413 #define CONFIG_PCI_SCAN_SHOW 414 #define CONFIG_CMD_PCI 415 #endif 416 417 #define CONFIG_CMDLINE_TAG 418 #define CONFIG_CMDLINE_EDITING 419 420 #define CONFIG_ARMV7_NONSEC 421 #define CONFIG_ARMV7_VIRT 422 #define CONFIG_PEN_ADDR_BIG_ENDIAN 423 #define CONFIG_LAYERSCAPE_NS_ACCESS 424 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 425 #define CONFIG_TIMER_CLK_FREQ 12500000 426 427 #define CONFIG_HWCONFIG 428 #define HWCONFIG_BUFFER_SIZE 256 429 430 #define CONFIG_FSL_DEVICE_DISABLE 431 432 433 #ifdef CONFIG_LPUART 434 #define CONFIG_EXTRA_ENV_SETTINGS \ 435 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 436 "initrd_high=0xffffffff\0" \ 437 "fdt_high=0xffffffff\0" 438 #else 439 #define CONFIG_EXTRA_ENV_SETTINGS \ 440 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 441 "initrd_high=0xffffffff\0" \ 442 "fdt_high=0xffffffff\0" 443 #endif 444 445 /* 446 * Miscellaneous configurable options 447 */ 448 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 449 #define CONFIG_AUTO_COMPLETE 450 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 451 #define CONFIG_SYS_PBSIZE \ 452 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 453 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 454 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 455 456 #define CONFIG_SYS_MEMTEST_START 0x80000000 457 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 458 459 #define CONFIG_SYS_LOAD_ADDR 0x82000000 460 461 #define CONFIG_LS102XA_STREAM_ID 462 463 /* 464 * Stack sizes 465 * The stack sizes are set up in start.S using the settings below 466 */ 467 #define CONFIG_STACKSIZE (30 * 1024) 468 469 #define CONFIG_SYS_INIT_SP_OFFSET \ 470 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 471 #define CONFIG_SYS_INIT_SP_ADDR \ 472 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 473 474 #ifdef CONFIG_SPL_BUILD 475 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 476 #else 477 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 478 #endif 479 480 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 481 482 /* 483 * Environment 484 */ 485 #define CONFIG_ENV_OVERWRITE 486 487 #if defined(CONFIG_SD_BOOT) 488 #define CONFIG_ENV_OFFSET 0x100000 489 #define CONFIG_ENV_IS_IN_MMC 490 #define CONFIG_SYS_MMC_ENV_DEV 0 491 #define CONFIG_ENV_SIZE 0x20000 492 #elif defined(CONFIG_QSPI_BOOT) 493 #define CONFIG_ENV_IS_IN_SPI_FLASH 494 #define CONFIG_ENV_SIZE 0x2000 495 #define CONFIG_ENV_OFFSET 0x100000 496 #define CONFIG_ENV_SECT_SIZE 0x10000 497 #else 498 #define CONFIG_ENV_IS_IN_FLASH 499 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 500 #define CONFIG_ENV_SIZE 0x20000 501 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 502 #endif 503 504 #define CONFIG_MISC_INIT_R 505 506 /* Hash command with SHA acceleration supported in hardware */ 507 #ifdef CONFIG_FSL_CAAM 508 #define CONFIG_CMD_HASH 509 #define CONFIG_SHA_HW_ACCEL 510 #endif 511 512 #include <asm/fsl_secure_boot.h> 513 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 514 515 #endif 516