1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3288_COMMON_H 8 #define __CONFIG_RK3288_COMMON_H 9 10 #include <asm/arch/hardware.h> 11 12 #define CONFIG_SYS_NO_FLASH 13 #define CONFIG_NR_DRAM_BANKS 1 14 #define CONFIG_ENV_SIZE 0x2000 15 #define CONFIG_SYS_MAXARGS 16 16 #define CONFIG_BAUDRATE 115200 17 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 18 #define CONFIG_SYS_CBSIZE 1024 19 #define CONFIG_SYS_THUMB_BUILD 20 #define CONFIG_DISPLAY_BOARDINFO 21 22 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 23 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ 24 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 25 26 #define CONFIG_SPL_FRAMEWORK 27 #define CONFIG_SPL_SERIAL_SUPPORT 28 #define CONFIG_SYS_NS16550_MEM32 29 #define CONFIG_SPL_BOARD_INIT 30 31 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 32 /* Bootrom will load u-boot binary to 0x0 once return from SPL */ 33 #define CONFIG_SYS_TEXT_BASE 0x00000000 34 #else 35 #define CONFIG_SYS_TEXT_BASE 0x00100000 36 #endif 37 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 38 #define CONFIG_SYS_LOAD_ADDR 0x00800800 39 #define CONFIG_SPL_STACK 0xff718000 40 #define CONFIG_SPL_TEXT_BASE 0xff704004 41 42 #define CONFIG_SILENT_CONSOLE 43 #ifndef CONFIG_SPL_BUILD 44 # define CONFIG_SYS_CONSOLE_IS_IN_ENV 45 # define CONFIG_CONSOLE_MUX 46 #endif 47 48 /* MMC/SD IP block */ 49 #define CONFIG_MMC 50 #define CONFIG_GENERIC_MMC 51 #define CONFIG_DWMMC 52 #define CONFIG_BOUNCE_BUFFER 53 54 #define CONFIG_FAT_WRITE 55 #define CONFIG_PARTITION_UUIDS 56 #define CONFIG_CMD_PART 57 58 /* RAW SD card / eMMC locations. */ 59 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 60 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 61 62 /* FAT sd card locations. */ 63 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 64 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 65 66 #define CONFIG_SPL_PINCTRL_SUPPORT 67 68 #define CONFIG_SYS_SDRAM_BASE 0 69 #define CONFIG_NR_DRAM_BANKS 1 70 #define SDRAM_BANK_SIZE (2UL << 30) 71 72 #define CONFIG_SPI_FLASH 73 #define CONFIG_SPI 74 #define CONFIG_SF_DEFAULT_SPEED 20000000 75 76 #ifndef CONFIG_SPL_BUILD 77 /* usb otg */ 78 #define CONFIG_USB_GADGET 79 #define CONFIG_USB_GADGET_DUALSPEED 80 #define CONFIG_USB_GADGET_DWC2_OTG 81 #define CONFIG_ROCKCHIP_USB2_PHY 82 #define CONFIG_USB_GADGET_VBUS_DRAW 0 83 84 /* fastboot */ 85 #define CONFIG_CMD_FASTBOOT 86 #define CONFIG_USB_FUNCTION_FASTBOOT 87 #define CONFIG_FASTBOOT_FLASH 88 #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ 89 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 90 #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 91 92 /* usb mass storage */ 93 #define CONFIG_USB_FUNCTION_MASS_STORAGE 94 #define CONFIG_CMD_USB_MASS_STORAGE 95 96 #define CONFIG_USB_GADGET_DOWNLOAD 97 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 98 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 99 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a 100 101 /* Enable gpt partition table */ 102 #define CONFIG_CMD_GPT 103 104 #include <config_distro_defaults.h> 105 106 #define ENV_MEM_LAYOUT_SETTINGS \ 107 "scriptaddr=0x00000000\0" \ 108 "pxefile_addr_r=0x00100000\0" \ 109 "fdt_addr_r=0x01f00000\0" \ 110 "kernel_addr_r=0x02000000\0" \ 111 "ramdisk_addr_r=0x04000000\0" 112 113 #define CONFIG_RANDOM_UUID 114 #define PARTS_DEFAULT \ 115 "uuid_disk=${uuid_gpt_disk};" \ 116 "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \ 117 "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ 118 119 /* First try to boot from SD (index 0), then eMMC (index 1 */ 120 #define BOOT_TARGET_DEVICES(func) \ 121 func(MMC, mmc, 0) \ 122 func(MMC, mmc, 1) 123 124 #include <config_distro_bootcmd.h> 125 126 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so 127 * limit the fdt reallocation to that */ 128 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 "fdt_high=0x1fffffff\0" \ 130 "initrd_high=0x1fffffff\0" \ 131 "partitions=" PARTS_DEFAULT \ 132 ENV_MEM_LAYOUT_SETTINGS \ 133 ROCKCHIP_DEVICE_SETTINGS \ 134 BOOTENV 135 #endif 136 137 #endif 138