1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x00201000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #define RESET_VECTOR_OFFSET 0x27FFC 56 #define BOOT_PAGE_OFFSET 0x27000 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_SKIP_RELOCATE 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 61 #define CONFIG_SYS_NO_FLASH 62 #endif 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 69 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_SPI_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_SUPPORT 78 #define CONFIG_SPL_SPI_FLASH_MINIMAL 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SPL_SPI_BOOT 88 #endif 89 90 #ifdef CONFIG_SDCARD 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 92 #define CONFIG_SPL_MMC_SUPPORT 93 #define CONFIG_SPL_MMC_MINIMAL 94 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 97 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_MMC_BOOT 103 #endif 104 105 #endif /* CONFIG_RAMBOOT_PBL */ 106 107 #ifndef CONFIG_SYS_TEXT_BASE 108 #define CONFIG_SYS_TEXT_BASE 0xeff40000 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #ifndef CONFIG_SYS_NO_FLASH 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 119 #endif 120 121 /* PCIe Boot - Master */ 122 #define CONFIG_SRIO_PCIE_BOOT_MASTER 123 /* 124 * for slave u-boot IMAGE instored in master memory space, 125 * PHYS must be aligned based on the SIZE 126 */ 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 132 #else 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 135 #endif 136 /* 137 * for slave UCODE and ENV instored in master memory space, 138 * PHYS must be aligned based on the SIZE 139 */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 143 #else 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 146 #endif 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 148 /* slave core release by master*/ 149 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 150 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 151 152 /* PCIe Boot - Slave */ 153 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 156 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 157 /* Set 1M boot space for PCIe boot */ 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 161 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 162 #define CONFIG_SYS_NO_FLASH 163 #endif 164 165 #if defined(CONFIG_SPIFLASH) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_SPI_FLASH 168 #define CONFIG_ENV_SPI_BUS 0 169 #define CONFIG_ENV_SPI_CS 0 170 #define CONFIG_ENV_SPI_MAX_HZ 10000000 171 #define CONFIG_ENV_SPI_MODE 0 172 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 173 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 174 #define CONFIG_ENV_SECT_SIZE 0x10000 175 #elif defined(CONFIG_SDCARD) 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_ENV_IS_IN_MMC 178 #define CONFIG_SYS_MMC_ENV_DEV 0 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_OFFSET (512 * 0x800) 181 #elif defined(CONFIG_NAND) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_NAND 184 #define CONFIG_ENV_SIZE 0x2000 185 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 186 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 187 #define CONFIG_ENV_IS_IN_REMOTE 188 #define CONFIG_ENV_ADDR 0xffe20000 189 #define CONFIG_ENV_SIZE 0x2000 190 #elif defined(CONFIG_ENV_IS_NOWHERE) 191 #define CONFIG_ENV_SIZE 0x2000 192 #else 193 #define CONFIG_ENV_IS_IN_FLASH 194 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 195 #define CONFIG_ENV_SIZE 0x2000 196 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 197 #endif 198 199 #ifndef __ASSEMBLY__ 200 unsigned long get_board_sys_clk(void); 201 unsigned long get_board_ddr_clk(void); 202 #endif 203 204 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 205 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 206 207 /* 208 * These can be toggled for performance analysis, otherwise use default. 209 */ 210 #define CONFIG_SYS_CACHE_STASHING 211 #define CONFIG_BACKSIDE_L2_CACHE 212 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 213 #define CONFIG_BTB /* toggle branch predition */ 214 #define CONFIG_DDR_ECC 215 #ifdef CONFIG_DDR_ECC 216 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 217 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 218 #endif 219 220 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 221 #define CONFIG_SYS_MEMTEST_END 0x00400000 222 #define CONFIG_SYS_ALT_MEMTEST 223 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 224 225 /* 226 * Config the L3 Cache as L3 SRAM 227 */ 228 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 229 #define CONFIG_SYS_L3_SIZE (256 << 10) 230 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 231 #ifdef CONFIG_RAMBOOT_PBL 232 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 233 #endif 234 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 235 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 236 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 237 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 238 239 #ifdef CONFIG_PHYS_64BIT 240 #define CONFIG_SYS_DCSRBAR 0xf0000000 241 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 242 #endif 243 244 /* EEPROM */ 245 #define CONFIG_ID_EEPROM 246 #define CONFIG_SYS_I2C_EEPROM_NXID 247 #define CONFIG_SYS_EEPROM_BUS_NUM 0 248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 252 253 /* 254 * DDR Setup 255 */ 256 #define CONFIG_VERY_BIG_RAM 257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 258 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 259 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 260 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 261 #define CONFIG_DDR_SPD 262 #ifndef CONFIG_SYS_FSL_DDR4 263 #define CONFIG_SYS_FSL_DDR3 264 #endif 265 266 #define CONFIG_SYS_SPD_BUS_NUM 0 267 #define SPD_EEPROM_ADDRESS 0x51 268 269 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 270 271 /* 272 * IFC Definitions 273 */ 274 #define CONFIG_SYS_FLASH_BASE 0xe0000000 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 277 #else 278 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 279 #endif 280 281 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 282 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 283 + 0x8000000) | \ 284 CSPR_PORT_SIZE_16 | \ 285 CSPR_MSEL_NOR | \ 286 CSPR_V) 287 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 288 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 289 CSPR_PORT_SIZE_16 | \ 290 CSPR_MSEL_NOR | \ 291 CSPR_V) 292 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 293 /* NOR Flash Timing Params */ 294 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 295 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 296 FTIM0_NOR_TEADC(0x5) | \ 297 FTIM0_NOR_TEAHC(0x5)) 298 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 299 FTIM1_NOR_TRAD_NOR(0x1A) |\ 300 FTIM1_NOR_TSEQRAD_NOR(0x13)) 301 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 302 FTIM2_NOR_TCH(0x4) | \ 303 FTIM2_NOR_TWPH(0x0E) | \ 304 FTIM2_NOR_TWP(0x1c)) 305 #define CONFIG_SYS_NOR_FTIM3 0x0 306 307 #define CONFIG_SYS_FLASH_QUIET_TEST 308 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 309 310 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 311 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 312 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 313 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 314 315 #define CONFIG_SYS_FLASH_EMPTY_INFO 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 317 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 318 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 319 #define QIXIS_BASE 0xffdf0000 320 #ifdef CONFIG_PHYS_64BIT 321 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 322 #else 323 #define QIXIS_BASE_PHYS QIXIS_BASE 324 #endif 325 #define QIXIS_LBMAP_SWITCH 0x06 326 #define QIXIS_LBMAP_MASK 0x0f 327 #define QIXIS_LBMAP_SHIFT 0 328 #define QIXIS_LBMAP_DFLTBANK 0x00 329 #define QIXIS_LBMAP_ALTBANK 0x04 330 #define QIXIS_RST_CTL_RESET 0x31 331 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 332 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 333 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 334 #define QIXIS_RST_FORCE_MEM 0x01 335 336 #define CONFIG_SYS_CSPR3_EXT (0xf) 337 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 338 | CSPR_PORT_SIZE_8 \ 339 | CSPR_MSEL_GPCM \ 340 | CSPR_V) 341 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 342 #define CONFIG_SYS_CSOR3 0x0 343 /* QIXIS Timing parameters for IFC CS3 */ 344 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 345 FTIM0_GPCM_TEADC(0x0e) | \ 346 FTIM0_GPCM_TEAHC(0x0e)) 347 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 348 FTIM1_GPCM_TRAD(0x3f)) 349 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 350 FTIM2_GPCM_TCH(0x8) | \ 351 FTIM2_GPCM_TWP(0x1f)) 352 #define CONFIG_SYS_CS3_FTIM3 0x0 353 354 #define CONFIG_NAND_FSL_IFC 355 #define CONFIG_SYS_NAND_BASE 0xff800000 356 #ifdef CONFIG_PHYS_64BIT 357 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 358 #else 359 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 360 #endif 361 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 362 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 363 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 364 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 365 | CSPR_V) 366 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 367 368 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 369 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 370 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 371 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 372 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 373 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 374 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 375 376 #define CONFIG_SYS_NAND_ONFI_DETECTION 377 378 /* ONFI NAND Flash mode0 Timing Params */ 379 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 380 FTIM0_NAND_TWP(0x18) | \ 381 FTIM0_NAND_TWCHT(0x07) | \ 382 FTIM0_NAND_TWH(0x0a)) 383 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 384 FTIM1_NAND_TWBE(0x39) | \ 385 FTIM1_NAND_TRR(0x0e) | \ 386 FTIM1_NAND_TRP(0x18)) 387 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 388 FTIM2_NAND_TREH(0x0a) | \ 389 FTIM2_NAND_TWHRE(0x1e)) 390 #define CONFIG_SYS_NAND_FTIM3 0x0 391 392 #define CONFIG_SYS_NAND_DDR_LAW 11 393 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 394 #define CONFIG_SYS_MAX_NAND_DEVICE 1 395 #define CONFIG_CMD_NAND 396 397 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 398 399 #if defined(CONFIG_NAND) 400 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 401 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 402 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 403 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 404 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 405 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 406 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 407 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 408 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 409 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 410 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 411 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 412 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 413 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 414 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 415 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 416 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 417 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 418 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #else 425 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 426 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 427 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 428 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 429 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 430 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 431 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 432 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 433 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 434 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 435 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 436 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 437 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 438 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 439 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 440 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 441 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 442 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 443 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 444 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 445 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 446 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 447 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 448 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 449 #endif 450 451 #ifdef CONFIG_SPL_BUILD 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 453 #else 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 455 #endif 456 457 #if defined(CONFIG_RAMBOOT_PBL) 458 #define CONFIG_SYS_RAMBOOT 459 #endif 460 461 #define CONFIG_BOARD_EARLY_INIT_R 462 #define CONFIG_MISC_INIT_R 463 464 #define CONFIG_HWCONFIG 465 466 /* define to use L1 as initial stack */ 467 #define CONFIG_L1_INIT_RAM 468 #define CONFIG_SYS_INIT_RAM_LOCK 469 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 473 /* The assembler doesn't like typecast */ 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 475 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 476 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 477 #else 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 481 #endif 482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 483 484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 485 GENERATED_GBL_DATA_SIZE) 486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 487 488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 489 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 490 491 /* Serial Port */ 492 #define CONFIG_CONS_INDEX 1 493 #define CONFIG_SYS_NS16550_SERIAL 494 #define CONFIG_SYS_NS16550_REG_SIZE 1 495 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 496 497 #define CONFIG_SYS_BAUDRATE_TABLE \ 498 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 499 500 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 501 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 502 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 503 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 504 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 505 506 /* Video */ 507 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 508 #define CONFIG_FSL_DIU_FB 509 #ifdef CONFIG_FSL_DIU_FB 510 #define CONFIG_FSL_DIU_CH7301 511 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 512 #define CONFIG_VIDEO 513 #define CONFIG_CMD_BMP 514 #define CONFIG_CFB_CONSOLE 515 #define CONFIG_VIDEO_SW_CURSOR 516 #define CONFIG_VGA_AS_SINGLE_DEVICE 517 #define CONFIG_VIDEO_LOGO 518 #define CONFIG_VIDEO_BMP_LOGO 519 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 520 /* 521 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 522 * disable empty flash sector detection, which is I/O-intensive. 523 */ 524 #undef CONFIG_SYS_FLASH_EMPTY_INFO 525 #endif 526 #endif 527 528 /* I2C */ 529 #define CONFIG_SYS_I2C 530 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 531 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 532 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 533 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 534 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 536 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 537 538 #define I2C_MUX_PCA_ADDR 0x77 539 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 540 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 541 #define I2C_RETIMER_ADDR 0x18 542 543 /* I2C bus multiplexer */ 544 #define I2C_MUX_CH_DEFAULT 0x8 545 #define I2C_MUX_CH_DIU 0xC 546 #define I2C_MUX_CH5 0xD 547 #define I2C_MUX_CH7 0xF 548 549 /* LDI/DVI Encoder for display */ 550 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 551 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 552 553 /* 554 * RTC configuration 555 */ 556 #define RTC 557 #define CONFIG_RTC_DS3231 1 558 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 559 560 /* 561 * eSPI - Enhanced SPI 562 */ 563 #ifndef CONFIG_SPL_BUILD 564 #endif 565 #define CONFIG_SPI_FLASH_BAR 566 #define CONFIG_SF_DEFAULT_SPEED 10000000 567 #define CONFIG_SF_DEFAULT_MODE 0 568 569 /* 570 * General PCIe 571 * Memory space is mapped 1-1, but I/O space must start from 0. 572 */ 573 #define CONFIG_PCI /* Enable PCI/PCIE */ 574 #define CONFIG_PCIE1 /* PCIE controller 1 */ 575 #define CONFIG_PCIE2 /* PCIE controller 2 */ 576 #define CONFIG_PCIE3 /* PCIE controller 3 */ 577 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 578 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 579 #define CONFIG_PCI_INDIRECT_BRIDGE 580 581 #ifdef CONFIG_PCI 582 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 583 #ifdef CONFIG_PCIE1 584 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 585 #ifdef CONFIG_PHYS_64BIT 586 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 588 #else 589 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 590 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 591 #endif 592 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 594 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 595 #ifdef CONFIG_PHYS_64BIT 596 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 597 #else 598 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 599 #endif 600 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 601 #endif 602 603 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 604 #ifdef CONFIG_PCIE2 605 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 606 #ifdef CONFIG_PHYS_64BIT 607 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 608 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 609 #else 610 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 611 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 612 #endif 613 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 614 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 615 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 616 #ifdef CONFIG_PHYS_64BIT 617 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 618 #else 619 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 620 #endif 621 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 622 #endif 623 624 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 625 #ifdef CONFIG_PCIE3 626 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 627 #ifdef CONFIG_PHYS_64BIT 628 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 629 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 630 #else 631 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 632 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 633 #endif 634 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 635 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 636 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 637 #ifdef CONFIG_PHYS_64BIT 638 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 639 #else 640 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 641 #endif 642 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 643 #endif 644 645 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 646 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 647 #define CONFIG_DOS_PARTITION 648 #endif /* CONFIG_PCI */ 649 650 /* 651 *SATA 652 */ 653 #define CONFIG_FSL_SATA_V2 654 #ifdef CONFIG_FSL_SATA_V2 655 #define CONFIG_LIBATA 656 #define CONFIG_FSL_SATA 657 #define CONFIG_SYS_SATA_MAX_DEVICE 1 658 #define CONFIG_SATA1 659 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 660 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 661 #define CONFIG_LBA48 662 #define CONFIG_CMD_SATA 663 #define CONFIG_DOS_PARTITION 664 #endif 665 666 /* 667 * USB 668 */ 669 #define CONFIG_HAS_FSL_DR_USB 670 671 #ifdef CONFIG_HAS_FSL_DR_USB 672 #define CONFIG_USB_EHCI 673 #define CONFIG_USB_EHCI_FSL 674 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 675 #endif 676 677 /* 678 * SDHC 679 */ 680 #define CONFIG_MMC 681 #ifdef CONFIG_MMC 682 #define CONFIG_FSL_ESDHC 683 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 684 #define CONFIG_GENERIC_MMC 685 #define CONFIG_DOS_PARTITION 686 #endif 687 688 /* Qman/Bman */ 689 #ifndef CONFIG_NOBQFMAN 690 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 691 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 692 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 693 #ifdef CONFIG_PHYS_64BIT 694 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 695 #else 696 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 697 #endif 698 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 699 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 700 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 701 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 702 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 703 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 704 CONFIG_SYS_BMAN_CENA_SIZE) 705 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 706 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 707 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 708 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 711 #else 712 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 713 #endif 714 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 715 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 716 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 717 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 718 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 719 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 720 CONFIG_SYS_QMAN_CENA_SIZE) 721 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 722 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 723 724 #define CONFIG_SYS_DPAA_FMAN 725 726 #define CONFIG_QE 727 #define CONFIG_U_QE 728 /* Default address of microcode for the Linux FMan driver */ 729 #if defined(CONFIG_SPIFLASH) 730 /* 731 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 732 * env, so we got 0x110000. 733 */ 734 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 735 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 736 #define CONFIG_SYS_QE_FW_ADDR 0x130000 737 #elif defined(CONFIG_SDCARD) 738 /* 739 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 740 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 741 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 742 */ 743 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 744 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 745 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 746 #elif defined(CONFIG_NAND) 747 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 748 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 749 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 750 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 751 /* 752 * Slave has no ucode locally, it can fetch this from remote. When implementing 753 * in two corenet boards, slave's ucode could be stored in master's memory 754 * space, the address can be mapped from slave TLB->slave LAW-> 755 * slave SRIO or PCIE outbound window->master inbound window-> 756 * master LAW->the ucode address in master's memory space. 757 */ 758 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 759 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 760 #else 761 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 762 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 763 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 764 #endif 765 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 766 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 767 #endif /* CONFIG_NOBQFMAN */ 768 769 #ifdef CONFIG_SYS_DPAA_FMAN 770 #define CONFIG_FMAN_ENET 771 #define CONFIG_PHYLIB_10G 772 #define CONFIG_PHY_VITESSE 773 #define CONFIG_PHY_REALTEK 774 #define CONFIG_PHY_TERANETICS 775 #define RGMII_PHY1_ADDR 0x1 776 #define RGMII_PHY2_ADDR 0x2 777 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 778 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 779 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 780 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 781 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 782 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 783 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 784 #endif 785 786 #ifdef CONFIG_FMAN_ENET 787 #define CONFIG_MII /* MII PHY management */ 788 #define CONFIG_ETHPRIME "FM1@DTSEC4" 789 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 790 #endif 791 792 /* 793 * Dynamic MTD Partition support with mtdparts 794 */ 795 #ifndef CONFIG_SYS_NO_FLASH 796 #define CONFIG_MTD_DEVICE 797 #define CONFIG_MTD_PARTITIONS 798 #define CONFIG_CMD_MTDPARTS 799 #define CONFIG_FLASH_CFI_MTD 800 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 801 "spi0=spife110000.0" 802 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 803 "128k(dtb),96m(fs),-(user);"\ 804 "fff800000.flash:2m(uboot),9m(kernel),"\ 805 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 806 "2m(uboot),9m(kernel),128k(dtb),-(user)" 807 #endif 808 809 /* 810 * Environment 811 */ 812 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 813 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 814 815 /* 816 * Command line configuration. 817 */ 818 #define CONFIG_CMD_DATE 819 #define CONFIG_CMD_EEPROM 820 #define CONFIG_CMD_ERRATA 821 #define CONFIG_CMD_IRQ 822 #define CONFIG_CMD_REGINFO 823 824 #ifdef CONFIG_PCI 825 #define CONFIG_CMD_PCI 826 #endif 827 828 /* 829 * Miscellaneous configurable options 830 */ 831 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 832 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 833 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 834 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 835 #ifdef CONFIG_CMD_KGDB 836 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 837 #else 838 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 839 #endif 840 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 841 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 842 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 843 844 /* 845 * For booting Linux, the board info and command line data 846 * have to be in the first 64 MB of memory, since this is 847 * the maximum mapped by the Linux kernel during initialization. 848 */ 849 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 850 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 851 852 #ifdef CONFIG_CMD_KGDB 853 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 854 #endif 855 856 /* 857 * Environment Configuration 858 */ 859 #define CONFIG_ROOTPATH "/opt/nfsroot" 860 #define CONFIG_BOOTFILE "uImage" 861 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 862 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 863 #define CONFIG_BAUDRATE 115200 864 #define __USB_PHY_TYPE utmi 865 866 #define CONFIG_EXTRA_ENV_SETTINGS \ 867 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 868 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 869 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 870 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 871 "fdtfile=t1024qds/t1024qds.dtb\0" \ 872 "netdev=eth0\0" \ 873 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 874 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 875 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 876 "tftpflash=tftpboot $loadaddr $uboot && " \ 877 "protect off $ubootaddr +$filesize && " \ 878 "erase $ubootaddr +$filesize && " \ 879 "cp.b $loadaddr $ubootaddr $filesize && " \ 880 "protect on $ubootaddr +$filesize && " \ 881 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 882 "consoledev=ttyS0\0" \ 883 "ramdiskaddr=2000000\0" \ 884 "fdtaddr=d00000\0" \ 885 "bdev=sda3\0" 886 887 #define CONFIG_LINUX \ 888 "setenv bootargs root=/dev/ram rw " \ 889 "console=$consoledev,$baudrate $othbootargs;" \ 890 "setenv ramdiskaddr 0x02000000;" \ 891 "setenv fdtaddr 0x00c00000;" \ 892 "setenv loadaddr 0x1000000;" \ 893 "bootm $loadaddr $ramdiskaddr $fdtaddr" 894 895 #define CONFIG_NFSBOOTCOMMAND \ 896 "setenv bootargs root=/dev/nfs rw " \ 897 "nfsroot=$serverip:$rootpath " \ 898 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 899 "console=$consoledev,$baudrate $othbootargs;" \ 900 "tftp $loadaddr $bootfile;" \ 901 "tftp $fdtaddr $fdtfile;" \ 902 "bootm $loadaddr - $fdtaddr" 903 904 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 905 906 /* Hash command with SHA acceleration supported in hardware */ 907 #ifdef CONFIG_FSL_CAAM 908 #define CONFIG_CMD_HASH 909 #define CONFIG_SHA_HW_ACCEL 910 #endif 911 912 #include <asm/fsl_secure_boot.h> 913 914 #endif /* __T1024QDS_H */ 915