1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_INITRD_TAG 28 29 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 30 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 33 #define CONFIG_SPL_MAX_SIZE 2048 34 #define CONFIG_SPL_SERIAL_SUPPORT 35 36 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 37 #define CONFIG_SYS_TEXT_BASE 0x87e00000 38 39 #ifndef CONFIG_SPL_BUILD 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 #endif 42 43 /* 44 * Size of malloc() pool 45 */ 46 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 47 48 /* 49 * Hardware drivers 50 */ 51 52 #define CONFIG_MXC_UART 53 #define CONFIG_MXC_UART_BASE UART1_BASE 54 #define CONFIG_MXC_GPIO 55 56 #define CONFIG_HARD_SPI 57 #define CONFIG_MXC_SPI 58 #define CONFIG_DEFAULT_SPI_BUS 1 59 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 60 61 /* PMIC Controller */ 62 #define CONFIG_POWER 63 #define CONFIG_POWER_SPI 64 #define CONFIG_POWER_FSL 65 #define CONFIG_FSL_PMIC_BUS 1 66 #define CONFIG_FSL_PMIC_CS 2 67 #define CONFIG_FSL_PMIC_CLK 1000000 68 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 69 #define CONFIG_FSL_PMIC_BITLEN 32 70 #define CONFIG_RTC_MC13XXX 71 72 /* allow to overwrite serial and ethaddr */ 73 #define CONFIG_ENV_OVERWRITE 74 #define CONFIG_CONS_INDEX 1 75 #define CONFIG_BAUDRATE 115200 76 77 /*********************************************************** 78 * Command definition 79 ***********************************************************/ 80 #define CONFIG_CMD_DATE 81 #define CONFIG_CMD_NAND 82 83 #define CONFIG_BOARD_LATE_INIT 84 85 86 #define CONFIG_EXTRA_ENV_SETTINGS \ 87 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 88 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 89 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 90 "bootcmd=run bootcmd_net\0" \ 91 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 92 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 93 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 94 "nand erase 0x0 0x40000; " \ 95 "nand write 0x81000000 0x0 0x40000\0" 96 97 #define CONFIG_SMC911X 98 #define CONFIG_SMC911X_BASE 0xB6000000 99 #define CONFIG_SMC911X_32_BIT 100 101 /* 102 * Miscellaneous configurable options 103 */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 /* max number of command args */ 107 #define CONFIG_SYS_MAXARGS 16 108 /* Boot Argument Buffer Size */ 109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 110 111 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_START 0x80000000 113 #define CONFIG_SYS_MEMTEST_END 0x80010000 114 115 /* default load address */ 116 #define CONFIG_SYS_LOAD_ADDR 0x81000000 117 118 #define CONFIG_CMDLINE_EDITING 119 120 /*----------------------------------------------------------------------- 121 * Physical Memory Map 122 */ 123 #define CONFIG_NR_DRAM_BANKS 1 124 #define PHYS_SDRAM_1 CSD0_BASE 125 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 126 #define CONFIG_BOARD_EARLY_INIT_F 127 128 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 129 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 130 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 132 GENERATED_GBL_DATA_SIZE) 133 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 134 CONFIG_SYS_INIT_RAM_SIZE) 135 136 /*----------------------------------------------------------------------- 137 * FLASH and environment organization 138 */ 139 /* No NOR flash present */ 140 #define CONFIG_SYS_NO_FLASH 141 142 #define CONFIG_ENV_IS_IN_NAND 143 #define CONFIG_ENV_OFFSET 0x40000 144 #define CONFIG_ENV_OFFSET_REDUND 0x60000 145 #define CONFIG_ENV_SIZE (128 * 1024) 146 147 /* 148 * NAND driver 149 */ 150 #define CONFIG_NAND_MXC 151 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 154 #define CONFIG_MXC_NAND_HWECC 155 #define CONFIG_SYS_NAND_LARGEPAGE 156 157 /* NAND configuration for the NAND_SPL */ 158 159 /* Start copying real U-Boot from the second page */ 160 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 161 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 162 /* Load U-Boot to this address */ 163 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 164 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 165 166 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 167 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 168 #define CONFIG_SYS_NAND_PAGE_COUNT 64 169 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 171 172 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 173 #define CCM_CCMR_SETUP 0x074B0BF5 174 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 175 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 176 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 177 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 178 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 179 PLL_MFN(12)) 180 181 #define ESDMISC_MDDR_SETUP 0x00000004 182 #define ESDMISC_MDDR_RESET_DL 0x0000000c 183 #define ESDCFG0_MDDR_SETUP 0x006ac73a 184 185 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 186 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 187 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 188 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 189 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 190 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 191 #define ESDCTL_RW ESDCTL_SETTINGS 192 193 #endif /* __CONFIG_H */ 194