1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x30001000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #ifdef CONFIG_SECURE_BOOT 67 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 68 /* 69 * HDR would be appended at end of image and copied to DDR along 70 * with U-Boot image. 71 */ 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 73 CONFIG_U_BOOT_HDR_SIZE) 74 #else 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 76 #endif 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 81 #define CONFIG_SPL_NAND_BOOT 82 #endif 83 84 #ifdef CONFIG_SPIFLASH 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 86 #define CONFIG_SPL_SPI_SUPPORT 87 #define CONFIG_SPL_SPI_FLASH_SUPPORT 88 #define CONFIG_SPL_SPI_FLASH_MINIMAL 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 93 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 94 #ifndef CONFIG_SPL_BUILD 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #endif 97 #define CONFIG_SPL_SPI_BOOT 98 #endif 99 100 #ifdef CONFIG_SDCARD 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 102 #define CONFIG_SPL_MMC_MINIMAL 103 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 104 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 105 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 106 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 107 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 108 #ifndef CONFIG_SPL_BUILD 109 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 110 #endif 111 #define CONFIG_SPL_MMC_BOOT 112 #endif 113 114 #endif 115 116 /* High Level Configuration Options */ 117 #define CONFIG_BOOKE 118 #define CONFIG_E500MC /* BOOKE e500mc family */ 119 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 120 #define CONFIG_MP /* support multiple processors */ 121 122 /* support deep sleep */ 123 #define CONFIG_DEEP_SLEEP 124 #if defined(CONFIG_DEEP_SLEEP) 125 #define CONFIG_BOARD_EARLY_INIT_F 126 #define CONFIG_SILENT_CONSOLE 127 #endif 128 129 #ifndef CONFIG_SYS_TEXT_BASE 130 #define CONFIG_SYS_TEXT_BASE 0xeff40000 131 #endif 132 133 #ifndef CONFIG_RESET_VECTOR_ADDRESS 134 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 135 #endif 136 137 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 138 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 139 #define CONFIG_FSL_IFC /* Enable IFC Support */ 140 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 141 #define CONFIG_PCI /* Enable PCI/PCIE */ 142 #define CONFIG_PCI_INDIRECT_BRIDGE 143 #define CONFIG_PCIE1 /* PCIE controller 1 */ 144 #define CONFIG_PCIE2 /* PCIE controller 2 */ 145 #define CONFIG_PCIE3 /* PCIE controller 3 */ 146 #define CONFIG_PCIE4 /* PCIE controller 4 */ 147 148 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 149 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 150 151 #define CONFIG_FSL_LAW /* Use common FSL init code */ 152 153 #define CONFIG_ENV_OVERWRITE 154 155 #ifndef CONFIG_SYS_NO_FLASH 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_CFI 158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 159 #endif 160 161 #if defined(CONFIG_SPIFLASH) 162 #define CONFIG_SYS_EXTRA_ENV_RELOC 163 #define CONFIG_ENV_IS_IN_SPI_FLASH 164 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 165 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 166 #define CONFIG_ENV_SECT_SIZE 0x10000 167 #elif defined(CONFIG_SDCARD) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_MMC 170 #define CONFIG_SYS_MMC_ENV_DEV 0 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_OFFSET (512 * 0x800) 173 #elif defined(CONFIG_NAND) 174 #ifdef CONFIG_SECURE_BOOT 175 #define CONFIG_RAMBOOT_NAND 176 #define CONFIG_BOOTSCRIPT_COPY_RAM 177 #endif 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_ENV_IS_IN_NAND 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 182 #else 183 #define CONFIG_ENV_IS_IN_FLASH 184 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 187 #endif 188 189 #define CONFIG_SYS_CLK_FREQ 100000000 190 #define CONFIG_DDR_CLK_FREQ 66666666 191 192 /* 193 * These can be toggled for performance analysis, otherwise use default. 194 */ 195 #define CONFIG_SYS_CACHE_STASHING 196 #define CONFIG_BACKSIDE_L2_CACHE 197 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 198 #define CONFIG_BTB /* toggle branch predition */ 199 #define CONFIG_DDR_ECC 200 #ifdef CONFIG_DDR_ECC 201 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 202 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 203 #endif 204 205 #define CONFIG_ENABLE_36BIT_PHYS 206 207 #define CONFIG_ADDR_MAP 208 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 209 210 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 211 #define CONFIG_SYS_MEMTEST_END 0x00400000 212 #define CONFIG_SYS_ALT_MEMTEST 213 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 214 215 /* 216 * Config the L3 Cache as L3 SRAM 217 */ 218 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 219 /* 220 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 221 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 222 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 223 */ 224 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 225 #define CONFIG_SYS_L3_SIZE 256 << 10 226 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 227 #ifdef CONFIG_RAMBOOT_PBL 228 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 229 #endif 230 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 231 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 232 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 233 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 234 235 #define CONFIG_SYS_DCSRBAR 0xf0000000 236 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 237 238 /* 239 * DDR Setup 240 */ 241 #define CONFIG_VERY_BIG_RAM 242 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 243 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 244 245 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 246 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 247 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 248 249 #define CONFIG_DDR_SPD 250 #ifndef CONFIG_SYS_FSL_DDR4 251 #define CONFIG_SYS_FSL_DDR3 252 #endif 253 254 #define CONFIG_SYS_SPD_BUS_NUM 0 255 #define SPD_EEPROM_ADDRESS 0x51 256 257 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 258 259 /* 260 * IFC Definitions 261 */ 262 #define CONFIG_SYS_FLASH_BASE 0xe8000000 263 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 264 265 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 266 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 267 CSPR_PORT_SIZE_16 | \ 268 CSPR_MSEL_NOR | \ 269 CSPR_V) 270 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 271 272 /* 273 * TDM Definition 274 */ 275 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 276 277 /* NOR Flash Timing Params */ 278 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 279 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 280 FTIM0_NOR_TEADC(0x5) | \ 281 FTIM0_NOR_TEAHC(0x5)) 282 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 283 FTIM1_NOR_TRAD_NOR(0x1A) |\ 284 FTIM1_NOR_TSEQRAD_NOR(0x13)) 285 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 286 FTIM2_NOR_TCH(0x4) | \ 287 FTIM2_NOR_TWPH(0x0E) | \ 288 FTIM2_NOR_TWP(0x1c)) 289 #define CONFIG_SYS_NOR_FTIM3 0x0 290 291 #define CONFIG_SYS_FLASH_QUIET_TEST 292 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 293 294 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 295 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 296 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 297 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 298 299 #define CONFIG_SYS_FLASH_EMPTY_INFO 300 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 301 302 /* CPLD on IFC */ 303 #define CPLD_LBMAP_MASK 0x3F 304 #define CPLD_BANK_SEL_MASK 0x07 305 #define CPLD_BANK_OVERRIDE 0x40 306 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 307 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 308 #define CPLD_LBMAP_RESET 0xFF 309 #define CPLD_LBMAP_SHIFT 0x03 310 311 #if defined(CONFIG_T1042RDB_PI) 312 #define CPLD_DIU_SEL_DFP 0x80 313 #elif defined(CONFIG_T1042D4RDB) 314 #define CPLD_DIU_SEL_DFP 0xc0 315 #endif 316 317 #if defined(CONFIG_T1040D4RDB) 318 #define CPLD_INT_MASK_ALL 0xFF 319 #define CPLD_INT_MASK_THERM 0x80 320 #define CPLD_INT_MASK_DVI_DFP 0x40 321 #define CPLD_INT_MASK_QSGMII1 0x20 322 #define CPLD_INT_MASK_QSGMII2 0x10 323 #define CPLD_INT_MASK_SGMI1 0x08 324 #define CPLD_INT_MASK_SGMI2 0x04 325 #define CPLD_INT_MASK_TDMR1 0x02 326 #define CPLD_INT_MASK_TDMR2 0x01 327 #endif 328 329 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 330 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 331 #define CONFIG_SYS_CSPR2_EXT (0xf) 332 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 333 | CSPR_PORT_SIZE_8 \ 334 | CSPR_MSEL_GPCM \ 335 | CSPR_V) 336 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 337 #define CONFIG_SYS_CSOR2 0x0 338 /* CPLD Timing parameters for IFC CS2 */ 339 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 340 FTIM0_GPCM_TEADC(0x0e) | \ 341 FTIM0_GPCM_TEAHC(0x0e)) 342 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 343 FTIM1_GPCM_TRAD(0x1f)) 344 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 345 FTIM2_GPCM_TCH(0x8) | \ 346 FTIM2_GPCM_TWP(0x1f)) 347 #define CONFIG_SYS_CS2_FTIM3 0x0 348 349 /* NAND Flash on IFC */ 350 #define CONFIG_NAND_FSL_IFC 351 #define CONFIG_SYS_NAND_BASE 0xff800000 352 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 353 354 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 355 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 356 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 357 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 358 | CSPR_V) 359 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 360 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 365 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 366 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 367 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 368 369 #define CONFIG_SYS_NAND_ONFI_DETECTION 370 371 /* ONFI NAND Flash mode0 Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 373 FTIM0_NAND_TWP(0x18) | \ 374 FTIM0_NAND_TWCHT(0x07) | \ 375 FTIM0_NAND_TWH(0x0a)) 376 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 377 FTIM1_NAND_TWBE(0x39) | \ 378 FTIM1_NAND_TRR(0x0e) | \ 379 FTIM1_NAND_TRP(0x18)) 380 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 381 FTIM2_NAND_TREH(0x0a) | \ 382 FTIM2_NAND_TWHRE(0x1e)) 383 #define CONFIG_SYS_NAND_FTIM3 0x0 384 385 #define CONFIG_SYS_NAND_DDR_LAW 11 386 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 387 #define CONFIG_SYS_MAX_NAND_DEVICE 1 388 #define CONFIG_CMD_NAND 389 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 391 392 #if defined(CONFIG_NAND) 393 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 394 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 395 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 396 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 397 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 398 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 399 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 400 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 401 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 402 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 403 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 404 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 405 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 406 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 407 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 408 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 409 #else 410 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 411 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 412 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 413 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 414 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 415 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 416 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 417 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 418 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 419 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 420 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 421 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 422 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 423 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 424 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 425 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 426 #endif 427 428 #ifdef CONFIG_SPL_BUILD 429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 430 #else 431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 432 #endif 433 434 #if defined(CONFIG_RAMBOOT_PBL) 435 #define CONFIG_SYS_RAMBOOT 436 #endif 437 438 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 439 #if defined(CONFIG_NAND) 440 #define CONFIG_A008044_WORKAROUND 441 #endif 442 #endif 443 444 #define CONFIG_BOARD_EARLY_INIT_R 445 #define CONFIG_MISC_INIT_R 446 447 #define CONFIG_HWCONFIG 448 449 /* define to use L1 as initial stack */ 450 #define CONFIG_L1_INIT_RAM 451 #define CONFIG_SYS_INIT_RAM_LOCK 452 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 455 /* The assembler doesn't like typecast */ 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 457 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 458 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 459 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 460 461 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 462 GENERATED_GBL_DATA_SIZE) 463 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 464 465 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 466 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 467 468 /* Serial Port - controlled on board with jumper J8 469 * open - index 2 470 * shorted - index 1 471 */ 472 #define CONFIG_CONS_INDEX 1 473 #define CONFIG_SYS_NS16550_SERIAL 474 #define CONFIG_SYS_NS16550_REG_SIZE 1 475 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 476 477 #define CONFIG_SYS_BAUDRATE_TABLE \ 478 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 479 480 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 481 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 482 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 483 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 484 #ifndef CONFIG_SPL_BUILD 485 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 486 #endif 487 488 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 489 /* Video */ 490 #define CONFIG_FSL_DIU_FB 491 492 #ifdef CONFIG_FSL_DIU_FB 493 #define CONFIG_FSL_DIU_CH7301 494 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 495 #define CONFIG_VIDEO 496 #define CONFIG_CMD_BMP 497 #define CONFIG_CFB_CONSOLE 498 #define CONFIG_CFB_CONSOLE_ANSI 499 #define CONFIG_VIDEO_SW_CURSOR 500 #define CONFIG_VGA_AS_SINGLE_DEVICE 501 #define CONFIG_VIDEO_LOGO 502 #define CONFIG_VIDEO_BMP_LOGO 503 #endif 504 #endif 505 506 /* I2C */ 507 #define CONFIG_SYS_I2C 508 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 509 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 510 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 511 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 512 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 518 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 519 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 520 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 521 522 /* I2C bus multiplexer */ 523 #define I2C_MUX_PCA_ADDR 0x70 524 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 525 #define I2C_MUX_CH_DEFAULT 0x8 526 #endif 527 528 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 529 /* LDI/DVI Encoder for display */ 530 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 531 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 532 533 /* 534 * RTC configuration 535 */ 536 #define RTC 537 #define CONFIG_RTC_DS1337 1 538 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 539 540 /*DVI encoder*/ 541 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 542 #endif 543 544 /* 545 * eSPI - Enhanced SPI 546 */ 547 #define CONFIG_SPI_FLASH_BAR 548 #define CONFIG_SF_DEFAULT_SPEED 10000000 549 #define CONFIG_SF_DEFAULT_MODE 0 550 #define CONFIG_ENV_SPI_BUS 0 551 #define CONFIG_ENV_SPI_CS 0 552 #define CONFIG_ENV_SPI_MAX_HZ 10000000 553 #define CONFIG_ENV_SPI_MODE 0 554 555 /* 556 * General PCI 557 * Memory space is mapped 1-1, but I/O space must start from 0. 558 */ 559 560 #ifdef CONFIG_PCI 561 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 562 #ifdef CONFIG_PCIE1 563 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 564 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 566 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 568 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 570 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 571 #endif 572 573 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 574 #ifdef CONFIG_PCIE2 575 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 576 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 577 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 578 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 580 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 581 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 582 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 583 #endif 584 585 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 586 #ifdef CONFIG_PCIE3 587 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 588 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 589 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 590 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 592 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 593 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 594 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 595 #endif 596 597 /* controller 4, Base address 203000 */ 598 #ifdef CONFIG_PCIE4 599 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 600 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 601 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 602 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 603 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 604 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 605 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 606 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 607 #endif 608 609 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 610 611 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 612 #define CONFIG_DOS_PARTITION 613 #endif /* CONFIG_PCI */ 614 615 /* SATA */ 616 #define CONFIG_FSL_SATA_V2 617 #ifdef CONFIG_FSL_SATA_V2 618 #define CONFIG_LIBATA 619 #define CONFIG_FSL_SATA 620 621 #define CONFIG_SYS_SATA_MAX_DEVICE 1 622 #define CONFIG_SATA1 623 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 624 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 625 626 #define CONFIG_LBA48 627 #define CONFIG_CMD_SATA 628 #define CONFIG_DOS_PARTITION 629 #endif 630 631 /* 632 * USB 633 */ 634 #define CONFIG_HAS_FSL_DR_USB 635 636 #ifdef CONFIG_HAS_FSL_DR_USB 637 #define CONFIG_USB_EHCI 638 639 #ifdef CONFIG_USB_EHCI 640 #define CONFIG_USB_EHCI_FSL 641 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 642 #endif 643 #endif 644 645 #define CONFIG_MMC 646 647 #ifdef CONFIG_MMC 648 #define CONFIG_FSL_ESDHC 649 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 650 #define CONFIG_GENERIC_MMC 651 #define CONFIG_DOS_PARTITION 652 #endif 653 654 /* Qman/Bman */ 655 #ifndef CONFIG_NOBQFMAN 656 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 657 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 658 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 659 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 660 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 661 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 662 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 663 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 664 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 666 CONFIG_SYS_BMAN_CENA_SIZE) 667 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 668 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 669 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 670 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 671 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 672 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 673 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 674 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 675 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 676 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 677 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 678 CONFIG_SYS_QMAN_CENA_SIZE) 679 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 680 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 681 682 #define CONFIG_SYS_DPAA_FMAN 683 #define CONFIG_SYS_DPAA_PME 684 685 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 686 #define CONFIG_QE 687 #define CONFIG_U_QE 688 #endif 689 690 /* Default address of microcode for the Linux Fman driver */ 691 #if defined(CONFIG_SPIFLASH) 692 /* 693 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 694 * env, so we got 0x110000. 695 */ 696 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 697 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 698 #elif defined(CONFIG_SDCARD) 699 /* 700 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 701 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 702 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 703 */ 704 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 705 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 706 #elif defined(CONFIG_NAND) 707 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 708 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 709 #else 710 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 711 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 712 #endif 713 714 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 715 #if defined(CONFIG_SPIFLASH) 716 #define CONFIG_SYS_QE_FW_ADDR 0x130000 717 #elif defined(CONFIG_SDCARD) 718 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 719 #elif defined(CONFIG_NAND) 720 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 721 #else 722 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 723 #endif 724 #endif 725 726 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 727 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 728 #endif /* CONFIG_NOBQFMAN */ 729 730 #ifdef CONFIG_SYS_DPAA_FMAN 731 #define CONFIG_FMAN_ENET 732 #define CONFIG_PHY_VITESSE 733 #define CONFIG_PHY_REALTEK 734 #endif 735 736 #ifdef CONFIG_FMAN_ENET 737 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 738 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 739 #elif defined(CONFIG_T1040D4RDB) 740 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 741 #elif defined(CONFIG_T1042D4RDB) 742 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 743 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 744 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 745 #endif 746 747 #ifdef CONFIG_T104XD4RDB 748 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 749 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 750 #else 751 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 752 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 753 #endif 754 755 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 756 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 757 #define CONFIG_VSC9953 758 #define CONFIG_CMD_ETHSW 759 #ifdef CONFIG_T1040RDB 760 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 761 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 762 #else 763 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 764 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 765 #endif 766 #endif 767 768 #define CONFIG_MII /* MII PHY management */ 769 #define CONFIG_ETHPRIME "FM1@DTSEC4" 770 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 771 #endif 772 773 /* 774 * Environment 775 */ 776 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 777 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 778 779 /* 780 * Command line configuration. 781 */ 782 #ifdef CONFIG_T1042RDB_PI 783 #define CONFIG_CMD_DATE 784 #endif 785 #define CONFIG_CMD_ERRATA 786 #define CONFIG_CMD_IRQ 787 #define CONFIG_CMD_REGINFO 788 789 #ifdef CONFIG_PCI 790 #define CONFIG_CMD_PCI 791 #endif 792 793 /* Hash command with SHA acceleration supported in hardware */ 794 #ifdef CONFIG_FSL_CAAM 795 #define CONFIG_CMD_HASH 796 #define CONFIG_SHA_HW_ACCEL 797 #endif 798 799 /* 800 * Miscellaneous configurable options 801 */ 802 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 803 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 804 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 805 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 806 #ifdef CONFIG_CMD_KGDB 807 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 808 #else 809 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 810 #endif 811 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 812 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 813 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 814 815 /* 816 * For booting Linux, the board info and command line data 817 * have to be in the first 64 MB of memory, since this is 818 * the maximum mapped by the Linux kernel during initialization. 819 */ 820 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 821 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 822 823 #ifdef CONFIG_CMD_KGDB 824 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 825 #endif 826 827 /* 828 * Dynamic MTD Partition support with mtdparts 829 */ 830 #ifndef CONFIG_SYS_NO_FLASH 831 #define CONFIG_MTD_DEVICE 832 #define CONFIG_MTD_PARTITIONS 833 #define CONFIG_CMD_MTDPARTS 834 #define CONFIG_FLASH_CFI_MTD 835 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 836 "spi0=spife110000.0" 837 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 838 "128k(dtb),96m(fs),-(user);"\ 839 "fff800000.flash:2m(uboot),9m(kernel),"\ 840 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 841 "2m(uboot),9m(kernel),128k(dtb),-(user)" 842 #endif 843 844 /* 845 * Environment Configuration 846 */ 847 #define CONFIG_ROOTPATH "/opt/nfsroot" 848 #define CONFIG_BOOTFILE "uImage" 849 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 850 851 /* default location for tftp and bootm */ 852 #define CONFIG_LOADADDR 1000000 853 854 855 #define CONFIG_BAUDRATE 115200 856 857 #define __USB_PHY_TYPE utmi 858 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 859 860 #ifdef CONFIG_T1040RDB 861 #define FDTFILE "t1040rdb/t1040rdb.dtb" 862 #elif defined(CONFIG_T1042RDB_PI) 863 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 864 #elif defined(CONFIG_T1042RDB) 865 #define FDTFILE "t1042rdb/t1042rdb.dtb" 866 #elif defined(CONFIG_T1040D4RDB) 867 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 868 #elif defined(CONFIG_T1042D4RDB) 869 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 870 #endif 871 872 #ifdef CONFIG_FSL_DIU_FB 873 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 874 #else 875 #define DIU_ENVIRONMENT 876 #endif 877 878 #define CONFIG_EXTRA_ENV_SETTINGS \ 879 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 880 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 881 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 882 "netdev=eth0\0" \ 883 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 884 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 885 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 886 "tftpflash=tftpboot $loadaddr $uboot && " \ 887 "protect off $ubootaddr +$filesize && " \ 888 "erase $ubootaddr +$filesize && " \ 889 "cp.b $loadaddr $ubootaddr $filesize && " \ 890 "protect on $ubootaddr +$filesize && " \ 891 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 892 "consoledev=ttyS0\0" \ 893 "ramdiskaddr=2000000\0" \ 894 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 895 "fdtaddr=1e00000\0" \ 896 "fdtfile=" __stringify(FDTFILE) "\0" \ 897 "bdev=sda3\0" 898 899 #define CONFIG_LINUX \ 900 "setenv bootargs root=/dev/ram rw " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "setenv ramdiskaddr 0x02000000;" \ 903 "setenv fdtaddr 0x00c00000;" \ 904 "setenv loadaddr 0x1000000;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr" 906 907 #define CONFIG_HDBOOT \ 908 "setenv bootargs root=/dev/$bdev rw " \ 909 "console=$consoledev,$baudrate $othbootargs;" \ 910 "tftp $loadaddr $bootfile;" \ 911 "tftp $fdtaddr $fdtfile;" \ 912 "bootm $loadaddr - $fdtaddr" 913 914 #define CONFIG_NFSBOOTCOMMAND \ 915 "setenv bootargs root=/dev/nfs rw " \ 916 "nfsroot=$serverip:$rootpath " \ 917 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 918 "console=$consoledev,$baudrate $othbootargs;" \ 919 "tftp $loadaddr $bootfile;" \ 920 "tftp $fdtaddr $fdtfile;" \ 921 "bootm $loadaddr - $fdtaddr" 922 923 #define CONFIG_RAMBOOTCOMMAND \ 924 "setenv bootargs root=/dev/ram rw " \ 925 "console=$consoledev,$baudrate $othbootargs;" \ 926 "tftp $ramdiskaddr $ramdiskfile;" \ 927 "tftp $loadaddr $bootfile;" \ 928 "tftp $fdtaddr $fdtfile;" \ 929 "bootm $loadaddr $ramdiskaddr $fdtaddr" 930 931 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 932 933 #include <asm/fsl_secure_boot.h> 934 935 #endif /* __CONFIG_H */ 936