1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 26 #ifdef CONFIG_NAND 27 #ifdef CONFIG_TPL_BUILD 28 #define CONFIG_SPL_NAND_BOOT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_NAND_INIT 31 #define CONFIG_TPL_SERIAL_SUPPORT 32 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_TPL_NAND_SUPPORT 34 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 35 #define CONFIG_SPL_COMMON_INIT_DDR 36 #define CONFIG_SPL_MAX_SIZE (128 << 10) 37 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 41 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 42 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 43 #elif defined(CONFIG_SPL_BUILD) 44 #define CONFIG_SPL_INIT_MINIMAL 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_NAND_SUPPORT 47 #define CONFIG_SPL_NAND_MINIMAL 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TEXT_BASE 0xff800000 50 #define CONFIG_SPL_MAX_SIZE 8192 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 55 #endif 56 #define CONFIG_SPL_PAD_TO 0x20000 57 #define CONFIG_TPL_PAD_TO 0x20000 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SYS_TEXT_BASE 0x11001000 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff40000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 #ifdef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 79 #endif 80 81 /* High Level Configuration Options */ 82 #define CONFIG_BOOKE /* BOOKE */ 83 #define CONFIG_E500 /* BOOKE e500 family */ 84 #define CONFIG_FSL_IFC /* Enable IFC Support */ 85 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 86 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 87 88 #define CONFIG_PCI /* Enable PCI/PCIE */ 89 #ifdef CONFIG_PCI 90 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 91 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 92 #define CONFIG_PCI_INDIRECT_BRIDGE 93 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 94 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 95 96 #define CONFIG_CMD_PCI 97 98 /* 99 * PCI Windows 100 * Memory space is mapped 1-1, but I/O space must start from 0. 101 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 103 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 105 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 106 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 107 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 108 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 109 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 110 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 111 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 112 113 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 114 115 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 116 #define CONFIG_DOS_PARTITION 117 #endif 118 119 #define CONFIG_FSL_LAW /* Use common FSL init code */ 120 #define CONFIG_TSEC_ENET 121 #define CONFIG_ENV_OVERWRITE 122 123 #define CONFIG_DDR_CLK_FREQ 100000000 124 #define CONFIG_SYS_CLK_FREQ 66666666 125 126 #define CONFIG_HWCONFIG 127 128 /* 129 * These can be toggled for performance analysis, otherwise use default. 130 */ 131 #define CONFIG_L2_CACHE /* toggle L2 cache */ 132 #define CONFIG_BTB /* toggle branch predition */ 133 134 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 135 136 #define CONFIG_ENABLE_36BIT_PHYS 137 138 #define CONFIG_ADDR_MAP 1 139 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 140 141 #define CONFIG_SYS_MEMTEST_START 0x00200000 142 #define CONFIG_SYS_MEMTEST_END 0x00400000 143 #define CONFIG_PANIC_HANG 144 145 /* DDR Setup */ 146 #define CONFIG_SYS_FSL_DDR3 147 #define CONFIG_DDR_SPD 148 #define CONFIG_SYS_SPD_BUS_NUM 0 149 #define SPD_EEPROM_ADDRESS 0x50 150 #define CONFIG_SYS_DDR_RAW_TIMING 151 152 /* DDR ECC Setup*/ 153 #define CONFIG_DDR_ECC 154 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 155 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 156 157 #define CONFIG_SYS_SDRAM_SIZE 512 158 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 160 161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 162 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 163 164 #define CONFIG_SYS_CCSRBAR 0xffe00000 165 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 166 167 /* Platform SRAM setting */ 168 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 169 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 170 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 171 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 172 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SYS_NO_FLASH 175 #endif 176 177 /* 178 * IFC Definitions 179 */ 180 /* NOR Flash on IFC */ 181 #define CONFIG_SYS_FLASH_BASE 0xec000000 182 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 183 184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 185 186 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 188 189 #define CONFIG_SYS_FLASH_QUIET_TEST 190 #define CONFIG_FLASH_SHOW_PROGRESS 45 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 193 194 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 195 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 196 CSPR_PORT_SIZE_16 | \ 197 CSPR_MSEL_NOR | \ 198 CSPR_V) 199 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 200 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 201 202 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 203 FTIM0_NOR_TEADC(0x5) | \ 204 FTIM0_NOR_TEAHC(0x5)) 205 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 206 FTIM1_NOR_TRAD_NOR(0x1A) |\ 207 FTIM1_NOR_TSEQRAD_NOR(0x13)) 208 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 209 FTIM2_NOR_TCH(0x4) | \ 210 FTIM2_NOR_TWPH(0x0E) | \ 211 FTIM2_NOR_TWP(0x1c)) 212 #define CONFIG_SYS_NOR_FTIM3 0x0 213 214 /* CFI for NOR Flash */ 215 #define CONFIG_FLASH_CFI_DRIVER 216 #define CONFIG_SYS_FLASH_CFI 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 219 220 /* NAND Flash on IFC */ 221 #define CONFIG_NAND_FSL_IFC 222 #define CONFIG_SYS_NAND_BASE 0xff800000 223 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 224 225 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 226 227 #define CONFIG_SYS_MAX_NAND_DEVICE 1 228 #define CONFIG_CMD_NAND 229 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 230 231 /* 8Bit NAND Flash - K9F1G08U0B */ 232 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 233 | CSPR_PORT_SIZE_8 \ 234 | CSPR_MSEL_NAND \ 235 | CSPR_V) 236 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 237 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 238 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 239 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 240 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 241 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 242 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 243 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 244 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 245 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 246 FTIM0_NAND_TWP(0x0c) | \ 247 FTIM0_NAND_TWCHT(0x08) | \ 248 FTIM0_NAND_TWH(0x06)) 249 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 250 FTIM1_NAND_TWBE(0x1d) | \ 251 FTIM1_NAND_TRR(0x08) | \ 252 FTIM1_NAND_TRP(0x0c)) 253 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 254 FTIM2_NAND_TREH(0x0a) | \ 255 FTIM2_NAND_TWHRE(0x18)) 256 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 257 258 #define CONFIG_SYS_NAND_DDR_LAW 11 259 260 /* Set up IFC registers for boot location NOR/NAND */ 261 #ifdef CONFIG_NAND 262 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 263 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 264 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 265 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 266 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 267 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 268 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 269 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 273 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 274 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 275 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 276 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 277 #else 278 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 279 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 280 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 281 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 282 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 283 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 284 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 285 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 286 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 287 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 288 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 289 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 290 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 291 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 292 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 293 #endif 294 295 /* CPLD on IFC, selected by CS2 */ 296 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 297 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 298 | CONFIG_SYS_CPLD_BASE) 299 300 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 301 | CSPR_PORT_SIZE_8 \ 302 | CSPR_MSEL_GPCM \ 303 | CSPR_V) 304 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 305 #define CONFIG_SYS_CSOR2 0x0 306 /* CPLD Timing parameters for IFC CS2 */ 307 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 308 FTIM0_GPCM_TEADC(0x0e) | \ 309 FTIM0_GPCM_TEAHC(0x0e)) 310 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 311 FTIM1_GPCM_TRAD(0x1f)) 312 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 313 FTIM2_GPCM_TCH(0x8) | \ 314 FTIM2_GPCM_TWP(0x1f)) 315 #define CONFIG_SYS_CS2_FTIM3 0x0 316 317 #if defined(CONFIG_RAMBOOT_SPIFLASH) 318 #define CONFIG_SYS_RAMBOOT 319 #define CONFIG_SYS_EXTRA_ENV_RELOC 320 #endif 321 322 #define CONFIG_BOARD_EARLY_INIT_R 323 324 #define CONFIG_SYS_INIT_RAM_LOCK 325 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 326 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 327 328 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 329 - GENERATED_GBL_DATA_SIZE) 330 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 331 332 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 333 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 334 335 /* 336 * Config the L2 Cache as L2 SRAM 337 */ 338 #if defined(CONFIG_SPL_BUILD) 339 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 340 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 341 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 342 #define CONFIG_SYS_L2_SIZE (256 << 10) 343 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 344 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 345 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 346 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 347 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 348 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 349 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 350 #elif defined(CONFIG_NAND) 351 #ifdef CONFIG_TPL_BUILD 352 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 353 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 354 #define CONFIG_SYS_L2_SIZE (256 << 10) 355 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 356 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 357 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 358 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 359 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 360 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 361 #else 362 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 363 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 364 #define CONFIG_SYS_L2_SIZE (256 << 10) 365 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 366 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 367 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 368 #endif 369 #endif 370 #endif 371 372 /* Serial Port */ 373 #define CONFIG_CONS_INDEX 1 374 #define CONFIG_SYS_NS16550_SERIAL 375 #define CONFIG_SYS_NS16550_REG_SIZE 1 376 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 377 378 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 379 #define CONFIG_NS16550_MIN_FUNCTIONS 380 #endif 381 382 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 383 384 #define CONFIG_SYS_BAUDRATE_TABLE \ 385 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 386 387 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 388 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 389 390 #define CONFIG_SYS_I2C 391 #define CONFIG_SYS_I2C_FSL 392 #define CONFIG_SYS_FSL_I2C_SPEED 400000 393 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 394 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 395 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 397 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 398 399 /* I2C EEPROM */ 400 /* enable read and write access to EEPROM */ 401 #define CONFIG_CMD_EEPROM 402 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 403 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 404 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 405 406 /* eSPI - Enhanced SPI */ 407 #define CONFIG_SF_DEFAULT_SPEED 10000000 408 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 409 410 #ifdef CONFIG_TSEC_ENET 411 #define CONFIG_MII /* MII PHY management */ 412 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 413 #define CONFIG_TSEC1 1 414 #define CONFIG_TSEC1_NAME "eTSEC1" 415 #define CONFIG_TSEC2 1 416 #define CONFIG_TSEC2_NAME "eTSEC2" 417 418 /* Default mode is RGMII mode */ 419 #define TSEC1_PHY_ADDR 0 420 #define TSEC2_PHY_ADDR 2 421 422 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 425 #define CONFIG_ETHPRIME "eTSEC1" 426 427 #define CONFIG_PHY_GIGE 428 #endif /* CONFIG_TSEC_ENET */ 429 430 /* 431 * Environment 432 */ 433 #if defined(CONFIG_SYS_RAMBOOT) 434 #if defined(CONFIG_RAMBOOT_SPIFLASH) 435 #define CONFIG_ENV_IS_IN_SPI_FLASH 436 #define CONFIG_ENV_SPI_BUS 0 437 #define CONFIG_ENV_SPI_CS 0 438 #define CONFIG_ENV_SPI_MAX_HZ 10000000 439 #define CONFIG_ENV_SPI_MODE 0 440 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 441 #define CONFIG_ENV_SECT_SIZE 0x10000 442 #define CONFIG_ENV_SIZE 0x2000 443 #endif 444 #elif defined(CONFIG_NAND) 445 #define CONFIG_ENV_IS_IN_NAND 446 #ifdef CONFIG_TPL_BUILD 447 #define CONFIG_ENV_SIZE 0x2000 448 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 449 #else 450 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 451 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 452 #endif 453 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 454 #else 455 #define CONFIG_ENV_IS_IN_FLASH 456 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 457 #define CONFIG_ENV_SIZE 0x2000 458 #define CONFIG_ENV_SECT_SIZE 0x20000 459 #endif 460 461 #define CONFIG_LOADS_ECHO 462 #define CONFIG_SYS_LOADS_BAUD_CHANGE 463 464 /* 465 * Command line configuration. 466 */ 467 #define CONFIG_CMD_ERRATA 468 #define CONFIG_CMD_IRQ 469 #define CONFIG_CMD_REGINFO 470 471 /* Hash command with SHA acceleration supported in hardware */ 472 #ifdef CONFIG_FSL_CAAM 473 #define CONFIG_CMD_HASH 474 #define CONFIG_SHA_HW_ACCEL 475 #endif 476 477 /* 478 * Miscellaneous configurable options 479 */ 480 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 481 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 482 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 483 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 484 485 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 487 /* Print Buffer Size */ 488 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 489 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 490 491 /* 492 * For booting Linux, the board info and command line data 493 * have to be in the first 64 MB of memory, since this is 494 * the maximum mapped by the Linux kernel during initialization. 495 */ 496 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 497 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 498 499 /* 500 * Environment Configuration 501 */ 502 503 #ifdef CONFIG_TSEC_ENET 504 #define CONFIG_HAS_ETH0 505 #define CONFIG_HAS_ETH1 506 #endif 507 508 #define CONFIG_ROOTPATH "/opt/nfsroot" 509 #define CONFIG_BOOTFILE "uImage" 510 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 511 512 /* default location for tftp and bootm */ 513 #define CONFIG_LOADADDR 1000000 514 515 516 #define CONFIG_BAUDRATE 115200 517 518 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 519 520 #define CONFIG_EXTRA_ENV_SETTINGS \ 521 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 522 "netdev=eth0\0" \ 523 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 524 "loadaddr=1000000\0" \ 525 "consoledev=ttyS0\0" \ 526 "ramdiskaddr=2000000\0" \ 527 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 528 "fdtaddr=1e00000\0" \ 529 "fdtfile=name/of/device-tree.dtb\0" \ 530 "othbootargs=ramdisk_size=600000\0" \ 531 532 #define CONFIG_RAMBOOTCOMMAND \ 533 "setenv bootargs root=/dev/ram rw " \ 534 "console=$consoledev,$baudrate $othbootargs; " \ 535 "tftp $ramdiskaddr $ramdiskfile;" \ 536 "tftp $loadaddr $bootfile;" \ 537 "tftp $fdtaddr $fdtfile;" \ 538 "bootm $loadaddr $ramdiskaddr $fdtaddr" 539 540 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 541 542 #include <asm/fsl_secure_boot.h> 543 544 #endif /* __CONFIG_H */ 545