1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_INITRD_TAG 28 29 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 30 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 33 #define CONFIG_SPL_MAX_SIZE 2048 34 #define CONFIG_SPL_NAND_SUPPORT 35 #define CONFIG_SPL_SERIAL_SUPPORT 36 37 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 38 #define CONFIG_SYS_TEXT_BASE 0x87e00000 39 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SKIP_LOWLEVEL_INIT 42 #endif 43 44 /* 45 * Size of malloc() pool 46 */ 47 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 48 49 /* 50 * Hardware drivers 51 */ 52 53 #define CONFIG_MXC_UART 54 #define CONFIG_MXC_UART_BASE UART1_BASE 55 #define CONFIG_MXC_GPIO 56 57 #define CONFIG_HARD_SPI 58 #define CONFIG_MXC_SPI 59 #define CONFIG_DEFAULT_SPI_BUS 1 60 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 61 62 /* PMIC Controller */ 63 #define CONFIG_POWER 64 #define CONFIG_POWER_SPI 65 #define CONFIG_POWER_FSL 66 #define CONFIG_FSL_PMIC_BUS 1 67 #define CONFIG_FSL_PMIC_CS 2 68 #define CONFIG_FSL_PMIC_CLK 1000000 69 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 70 #define CONFIG_FSL_PMIC_BITLEN 32 71 #define CONFIG_RTC_MC13XXX 72 73 /* allow to overwrite serial and ethaddr */ 74 #define CONFIG_ENV_OVERWRITE 75 #define CONFIG_CONS_INDEX 1 76 #define CONFIG_BAUDRATE 115200 77 78 /*********************************************************** 79 * Command definition 80 ***********************************************************/ 81 #define CONFIG_CMD_DATE 82 #define CONFIG_CMD_NAND 83 84 #define CONFIG_BOARD_LATE_INIT 85 86 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 89 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 90 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 91 "bootcmd=run bootcmd_net\0" \ 92 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 93 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 94 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 95 "nand erase 0x0 0x40000; " \ 96 "nand write 0x81000000 0x0 0x40000\0" 97 98 #define CONFIG_SMC911X 99 #define CONFIG_SMC911X_BASE 0xB6000000 100 #define CONFIG_SMC911X_32_BIT 101 102 /* 103 * Miscellaneous configurable options 104 */ 105 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 106 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 107 /* max number of command args */ 108 #define CONFIG_SYS_MAXARGS 16 109 /* Boot Argument Buffer Size */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 111 112 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_START 0x80000000 114 #define CONFIG_SYS_MEMTEST_END 0x80010000 115 116 /* default load address */ 117 #define CONFIG_SYS_LOAD_ADDR 0x81000000 118 119 #define CONFIG_CMDLINE_EDITING 120 121 /*----------------------------------------------------------------------- 122 * Physical Memory Map 123 */ 124 #define CONFIG_NR_DRAM_BANKS 1 125 #define PHYS_SDRAM_1 CSD0_BASE 126 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 127 #define CONFIG_BOARD_EARLY_INIT_F 128 129 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 130 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 131 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 132 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 133 GENERATED_GBL_DATA_SIZE) 134 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 135 CONFIG_SYS_INIT_RAM_SIZE) 136 137 /*----------------------------------------------------------------------- 138 * FLASH and environment organization 139 */ 140 /* No NOR flash present */ 141 #define CONFIG_SYS_NO_FLASH 142 143 #define CONFIG_ENV_IS_IN_NAND 144 #define CONFIG_ENV_OFFSET 0x40000 145 #define CONFIG_ENV_OFFSET_REDUND 0x60000 146 #define CONFIG_ENV_SIZE (128 * 1024) 147 148 /* 149 * NAND driver 150 */ 151 #define CONFIG_NAND_MXC 152 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 154 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 155 #define CONFIG_MXC_NAND_HWECC 156 #define CONFIG_SYS_NAND_LARGEPAGE 157 158 /* NAND configuration for the NAND_SPL */ 159 160 /* Start copying real U-Boot from the second page */ 161 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 162 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 163 /* Load U-Boot to this address */ 164 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 165 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 166 167 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 168 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 169 #define CONFIG_SYS_NAND_PAGE_COUNT 64 170 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 171 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 172 173 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 174 #define CCM_CCMR_SETUP 0x074B0BF5 175 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 176 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 177 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 178 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 179 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 180 PLL_MFN(12)) 181 182 #define ESDMISC_MDDR_SETUP 0x00000004 183 #define ESDMISC_MDDR_RESET_DL 0x0000000c 184 #define ESDCFG0_MDDR_SETUP 0x006ac73a 185 186 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 187 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 188 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 189 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 190 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 191 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 192 #define ESDCTL_RW ESDCTL_SETTINGS 193 194 #endif /* __CONFIG_H */ 195