1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SPL_WATCHDOG_SUPPORT 71 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 72 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 73 74 #define CONFIG_SPL_TEXT_BASE 0x10000000 75 #define CONFIG_SPL_MAX_SIZE 0x1a000 76 #define CONFIG_SPL_STACK 0x1001d000 77 #define CONFIG_SPL_PAD_TO 0x1c000 78 #define CONFIG_SYS_TEXT_BASE 0x82000000 79 80 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 81 CONFIG_SYS_MONITOR_LEN) 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_MONITOR_LEN 0xc0000 86 #endif 87 88 #ifdef CONFIG_QSPI_BOOT 89 #define CONFIG_SYS_TEXT_BASE 0x40010000 90 #endif 91 92 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 93 #define CONFIG_SYS_NO_FLASH 94 #endif 95 96 #ifdef CONFIG_NAND_BOOT 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 98 #define CONFIG_SPL_FRAMEWORK 99 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 100 #define CONFIG_SPL_WATCHDOG_SUPPORT 101 102 #define CONFIG_SPL_TEXT_BASE 0x10000000 103 #define CONFIG_SPL_MAX_SIZE 0x1a000 104 #define CONFIG_SPL_STACK 0x1001d000 105 #define CONFIG_SPL_PAD_TO 0x1c000 106 #define CONFIG_SYS_TEXT_BASE 0x82000000 107 108 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 109 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 110 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 111 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 112 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 113 114 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 115 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 116 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 117 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 118 #define CONFIG_SYS_MONITOR_LEN 0x80000 119 #endif 120 121 #ifndef CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_TEXT_BASE 0x60100000 123 #endif 124 125 #define CONFIG_NR_DRAM_BANKS 1 126 127 #define CONFIG_DDR_SPD 128 #define SPD_EEPROM_ADDRESS 0x51 129 #define CONFIG_SYS_SPD_BUS_NUM 0 130 131 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 132 #ifndef CONFIG_SYS_FSL_DDR4 133 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 134 #define CONFIG_SYS_DDR_RAW_TIMING 135 #endif 136 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 137 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 138 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_DDR_ECC 143 #ifdef CONFIG_DDR_ECC 144 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 145 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 146 #endif 147 148 #define CONFIG_SYS_HAS_SERDES 149 150 #define CONFIG_FSL_CAAM /* Enable CAAM */ 151 152 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 153 !defined(CONFIG_QSPI_BOOT) 154 #define CONFIG_U_QE 155 #endif 156 157 /* 158 * IFC Definitions 159 */ 160 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 161 #define CONFIG_FSL_IFC 162 #define CONFIG_SYS_FLASH_BASE 0x60000000 163 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 164 165 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 166 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 167 CSPR_PORT_SIZE_16 | \ 168 CSPR_MSEL_NOR | \ 169 CSPR_V) 170 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 171 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 172 + 0x8000000) | \ 173 CSPR_PORT_SIZE_16 | \ 174 CSPR_MSEL_NOR | \ 175 CSPR_V) 176 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 177 178 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 179 CSOR_NOR_TRHZ_80) 180 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 181 FTIM0_NOR_TEADC(0x5) | \ 182 FTIM0_NOR_TEAHC(0x5)) 183 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 184 FTIM1_NOR_TRAD_NOR(0x1a) | \ 185 FTIM1_NOR_TSEQRAD_NOR(0x13)) 186 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 187 FTIM2_NOR_TCH(0x4) | \ 188 FTIM2_NOR_TWPH(0xe) | \ 189 FTIM2_NOR_TWP(0x1c)) 190 #define CONFIG_SYS_NOR_FTIM3 0 191 192 #define CONFIG_FLASH_CFI_DRIVER 193 #define CONFIG_SYS_FLASH_CFI 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 197 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 198 #define CONFIG_SYS_WRITE_SWAPPED_DATA 199 200 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 201 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 204 205 #define CONFIG_SYS_FLASH_EMPTY_INFO 206 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 207 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 208 209 /* 210 * NAND Flash Definitions 211 */ 212 #define CONFIG_NAND_FSL_IFC 213 214 #define CONFIG_SYS_NAND_BASE 0x7e800000 215 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 216 217 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 218 219 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 220 | CSPR_PORT_SIZE_8 \ 221 | CSPR_MSEL_NAND \ 222 | CSPR_V) 223 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 224 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 225 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 226 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 227 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 228 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 229 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 230 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 231 232 #define CONFIG_SYS_NAND_ONFI_DETECTION 233 234 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 235 FTIM0_NAND_TWP(0x18) | \ 236 FTIM0_NAND_TWCHT(0x7) | \ 237 FTIM0_NAND_TWH(0xa)) 238 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 239 FTIM1_NAND_TWBE(0x39) | \ 240 FTIM1_NAND_TRR(0xe) | \ 241 FTIM1_NAND_TRP(0x18)) 242 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 243 FTIM2_NAND_TREH(0xa) | \ 244 FTIM2_NAND_TWHRE(0x1e)) 245 #define CONFIG_SYS_NAND_FTIM3 0x0 246 247 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_CMD_NAND 250 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 252 #endif 253 254 /* 255 * QIXIS Definitions 256 */ 257 #define CONFIG_FSL_QIXIS 258 259 #ifdef CONFIG_FSL_QIXIS 260 #define QIXIS_BASE 0x7fb00000 261 #define QIXIS_BASE_PHYS QIXIS_BASE 262 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 263 #define QIXIS_LBMAP_SWITCH 6 264 #define QIXIS_LBMAP_MASK 0x0f 265 #define QIXIS_LBMAP_SHIFT 0 266 #define QIXIS_LBMAP_DFLTBANK 0x00 267 #define QIXIS_LBMAP_ALTBANK 0x04 268 #define QIXIS_PWR_CTL 0x21 269 #define QIXIS_PWR_CTL_POWEROFF 0x80 270 #define QIXIS_RST_CTL_RESET 0x44 271 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 272 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 273 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 274 275 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 276 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 277 CSPR_PORT_SIZE_8 | \ 278 CSPR_MSEL_GPCM | \ 279 CSPR_V) 280 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 281 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 282 CSOR_NOR_NOR_MODE_AVD_NOR | \ 283 CSOR_NOR_TRHZ_80) 284 285 /* 286 * QIXIS Timing parameters for IFC GPCM 287 */ 288 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 289 FTIM0_GPCM_TEADC(0xe) | \ 290 FTIM0_GPCM_TEAHC(0xe)) 291 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 292 FTIM1_GPCM_TRAD(0x1f)) 293 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 294 FTIM2_GPCM_TCH(0xe) | \ 295 FTIM2_GPCM_TWP(0xf0)) 296 #define CONFIG_SYS_FPGA_FTIM3 0x0 297 #endif 298 299 #if defined(CONFIG_NAND_BOOT) 300 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 301 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 302 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 303 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 304 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 305 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 306 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 307 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 308 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 317 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 318 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 325 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 326 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 327 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 328 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 329 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 330 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 331 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 332 #else 333 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 342 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 343 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 344 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 345 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 346 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 347 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 348 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 349 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 350 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 358 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 359 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 360 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 361 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 362 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 363 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 364 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 365 #endif 366 367 /* 368 * Serial Port 369 */ 370 #ifdef CONFIG_LPUART 371 #define CONFIG_LPUART_32B_REG 372 #else 373 #define CONFIG_CONS_INDEX 1 374 #define CONFIG_SYS_NS16550_SERIAL 375 #ifndef CONFIG_DM_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #endif 378 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 379 #endif 380 381 #define CONFIG_BAUDRATE 115200 382 383 /* 384 * I2C 385 */ 386 #define CONFIG_SYS_I2C 387 #define CONFIG_SYS_I2C_MXC 388 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 389 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 390 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 391 392 /* 393 * I2C bus multiplexer 394 */ 395 #define I2C_MUX_PCA_ADDR_PRI 0x77 396 #define I2C_MUX_CH_DEFAULT 0x8 397 #define I2C_MUX_CH_CH7301 0xC 398 399 /* 400 * MMC 401 */ 402 #define CONFIG_MMC 403 #define CONFIG_FSL_ESDHC 404 #define CONFIG_GENERIC_MMC 405 406 #define CONFIG_DOS_PARTITION 407 408 /* SPI */ 409 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 410 /* QSPI */ 411 #define QSPI0_AMBA_BASE 0x40000000 412 #define FSL_QSPI_FLASH_SIZE (1 << 24) 413 #define FSL_QSPI_FLASH_NUM 2 414 415 /* DSPI */ 416 417 /* DM SPI */ 418 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 419 #define CONFIG_DM_SPI_FLASH 420 #define CONFIG_SPI_FLASH_DATAFLASH 421 #endif 422 #endif 423 424 /* 425 * USB 426 */ 427 /* EHCI Support - disbaled by default */ 428 /*#define CONFIG_HAS_FSL_DR_USB*/ 429 430 #ifdef CONFIG_HAS_FSL_DR_USB 431 #define CONFIG_USB_EHCI 432 #define CONFIG_USB_EHCI_FSL 433 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 434 #endif 435 436 /*XHCI Support - enabled by default*/ 437 #define CONFIG_HAS_FSL_XHCI_USB 438 439 #ifdef CONFIG_HAS_FSL_XHCI_USB 440 #define CONFIG_USB_XHCI_FSL 441 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 442 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 443 #endif 444 445 /* 446 * Video 447 */ 448 #define CONFIG_FSL_DCU_FB 449 450 #ifdef CONFIG_FSL_DCU_FB 451 #define CONFIG_VIDEO 452 #define CONFIG_CMD_BMP 453 #define CONFIG_CFB_CONSOLE 454 #define CONFIG_VGA_AS_SINGLE_DEVICE 455 #define CONFIG_VIDEO_LOGO 456 #define CONFIG_VIDEO_BMP_LOGO 457 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 458 459 #define CONFIG_FSL_DIU_CH7301 460 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 461 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 462 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 463 #endif 464 465 /* 466 * eTSEC 467 */ 468 #define CONFIG_TSEC_ENET 469 470 #ifdef CONFIG_TSEC_ENET 471 #define CONFIG_MII 472 #define CONFIG_MII_DEFAULT_TSEC 3 473 #define CONFIG_TSEC1 1 474 #define CONFIG_TSEC1_NAME "eTSEC1" 475 #define CONFIG_TSEC2 1 476 #define CONFIG_TSEC2_NAME "eTSEC2" 477 #define CONFIG_TSEC3 1 478 #define CONFIG_TSEC3_NAME "eTSEC3" 479 480 #define TSEC1_PHY_ADDR 1 481 #define TSEC2_PHY_ADDR 2 482 #define TSEC3_PHY_ADDR 3 483 484 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 485 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 486 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 487 488 #define TSEC1_PHYIDX 0 489 #define TSEC2_PHYIDX 0 490 #define TSEC3_PHYIDX 0 491 492 #define CONFIG_ETHPRIME "eTSEC1" 493 494 #define CONFIG_PHY_GIGE 495 #define CONFIG_PHYLIB 496 #define CONFIG_PHY_REALTEK 497 498 #define CONFIG_HAS_ETH0 499 #define CONFIG_HAS_ETH1 500 #define CONFIG_HAS_ETH2 501 502 #define CONFIG_FSL_SGMII_RISER 1 503 #define SGMII_RISER_PHY_OFFSET 0x1b 504 505 #ifdef CONFIG_FSL_SGMII_RISER 506 #define CONFIG_SYS_TBIPA_VALUE 8 507 #endif 508 509 #endif 510 511 /* PCIe */ 512 #define CONFIG_PCI /* Enable PCI/PCIE */ 513 #define CONFIG_PCIE1 /* PCIE controller 1 */ 514 #define CONFIG_PCIE2 /* PCIE controller 2 */ 515 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 516 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 517 518 #define CONFIG_SYS_PCI_64BIT 519 520 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 521 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 522 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 523 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 524 525 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 526 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 527 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 528 529 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 530 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 531 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 532 533 #ifdef CONFIG_PCI 534 #define CONFIG_PCI_PNP 535 #define CONFIG_PCI_SCAN_SHOW 536 #define CONFIG_CMD_PCI 537 #endif 538 539 #define CONFIG_CMDLINE_TAG 540 #define CONFIG_CMDLINE_EDITING 541 542 #define CONFIG_ARMV7_NONSEC 543 #define CONFIG_ARMV7_VIRT 544 #define CONFIG_PEN_ADDR_BIG_ENDIAN 545 #define CONFIG_LAYERSCAPE_NS_ACCESS 546 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 547 #define CONFIG_TIMER_CLK_FREQ 12500000 548 549 #define CONFIG_HWCONFIG 550 #define HWCONFIG_BUFFER_SIZE 256 551 552 #define CONFIG_FSL_DEVICE_DISABLE 553 554 555 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 556 557 #ifdef CONFIG_LPUART 558 #define CONFIG_EXTRA_ENV_SETTINGS \ 559 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 560 "fdt_high=0xffffffff\0" \ 561 "initrd_high=0xffffffff\0" \ 562 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 563 #else 564 #define CONFIG_EXTRA_ENV_SETTINGS \ 565 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 566 "fdt_high=0xffffffff\0" \ 567 "initrd_high=0xffffffff\0" \ 568 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 569 #endif 570 571 /* 572 * Miscellaneous configurable options 573 */ 574 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 575 #define CONFIG_AUTO_COMPLETE 576 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 577 #define CONFIG_SYS_PBSIZE \ 578 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 579 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 580 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 581 582 #define CONFIG_SYS_MEMTEST_START 0x80000000 583 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 584 585 #define CONFIG_SYS_LOAD_ADDR 0x82000000 586 587 #define CONFIG_LS102XA_STREAM_ID 588 589 /* 590 * Stack sizes 591 * The stack sizes are set up in start.S using the settings below 592 */ 593 #define CONFIG_STACKSIZE (30 * 1024) 594 595 #define CONFIG_SYS_INIT_SP_OFFSET \ 596 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 597 #define CONFIG_SYS_INIT_SP_ADDR \ 598 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 599 600 #ifdef CONFIG_SPL_BUILD 601 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 602 #else 603 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 604 #endif 605 606 /* 607 * Environment 608 */ 609 #define CONFIG_ENV_OVERWRITE 610 611 #if defined(CONFIG_SD_BOOT) 612 #define CONFIG_ENV_OFFSET 0x100000 613 #define CONFIG_ENV_IS_IN_MMC 614 #define CONFIG_SYS_MMC_ENV_DEV 0 615 #define CONFIG_ENV_SIZE 0x2000 616 #elif defined(CONFIG_QSPI_BOOT) 617 #define CONFIG_ENV_IS_IN_SPI_FLASH 618 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 619 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 620 #define CONFIG_ENV_SECT_SIZE 0x10000 621 #elif defined(CONFIG_NAND_BOOT) 622 #define CONFIG_ENV_IS_IN_NAND 623 #define CONFIG_ENV_SIZE 0x2000 624 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 625 #else 626 #define CONFIG_ENV_IS_IN_FLASH 627 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 628 #define CONFIG_ENV_SIZE 0x2000 629 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 630 #endif 631 632 #define CONFIG_MISC_INIT_R 633 634 /* Hash command with SHA acceleration supported in hardware */ 635 #ifdef CONFIG_FSL_CAAM 636 #define CONFIG_CMD_HASH 637 #define CONFIG_SHA_HW_ACCEL 638 #endif 639 640 #include <asm/fsl_secure_boot.h> 641 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 642 643 #endif 644