1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_SERIAL_SUPPORT 185 #define CONFIG_SPL_MMC_MINIMAL 186 #define CONFIG_SPL_FLUSH_IMAGE 187 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 188 #define CONFIG_FSL_LAW /* Use common FSL init code */ 189 #define CONFIG_SYS_TEXT_BASE 0x11001000 190 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 191 #define CONFIG_SPL_PAD_TO 0x20000 192 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 193 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 194 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 195 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 196 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 197 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 198 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 199 #define CONFIG_SPL_MMC_BOOT 200 #ifdef CONFIG_SPL_BUILD 201 #define CONFIG_SPL_COMMON_INIT_DDR 202 #endif 203 #endif 204 205 #ifdef CONFIG_SPIFLASH 206 #define CONFIG_SPL_SERIAL_SUPPORT 207 #define CONFIG_SPL_SPI_SUPPORT 208 #define CONFIG_SPL_SPI_FLASH_SUPPORT 209 #define CONFIG_SPL_SPI_FLASH_MINIMAL 210 #define CONFIG_SPL_FLUSH_IMAGE 211 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 212 #define CONFIG_FSL_LAW /* Use common FSL init code */ 213 #define CONFIG_SYS_TEXT_BASE 0x11001000 214 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 215 #define CONFIG_SPL_PAD_TO 0x20000 216 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 217 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 218 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 219 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 220 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 221 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 222 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 223 #define CONFIG_SPL_SPI_BOOT 224 #ifdef CONFIG_SPL_BUILD 225 #define CONFIG_SPL_COMMON_INIT_DDR 226 #endif 227 #endif 228 229 #ifdef CONFIG_NAND 230 #ifdef CONFIG_TPL_BUILD 231 #define CONFIG_SPL_NAND_BOOT 232 #define CONFIG_SPL_FLUSH_IMAGE 233 #define CONFIG_SPL_NAND_INIT 234 #define CONFIG_TPL_SERIAL_SUPPORT 235 #define CONFIG_SPL_COMMON_INIT_DDR 236 #define CONFIG_SPL_MAX_SIZE (128 << 10) 237 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 238 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 239 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 240 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 241 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 242 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 243 #elif defined(CONFIG_SPL_BUILD) 244 #define CONFIG_SPL_INIT_MINIMAL 245 #define CONFIG_SPL_SERIAL_SUPPORT 246 #define CONFIG_SPL_FLUSH_IMAGE 247 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 248 #define CONFIG_SPL_TEXT_BASE 0xff800000 249 #define CONFIG_SPL_MAX_SIZE 4096 250 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 251 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 252 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 253 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 254 #endif /* not CONFIG_TPL_BUILD */ 255 256 #define CONFIG_SPL_PAD_TO 0x20000 257 #define CONFIG_TPL_PAD_TO 0x20000 258 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 259 #define CONFIG_SYS_TEXT_BASE 0x11001000 260 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 261 #endif 262 263 #ifndef CONFIG_SYS_TEXT_BASE 264 #define CONFIG_SYS_TEXT_BASE 0xeff40000 265 #endif 266 267 #ifndef CONFIG_RESET_VECTOR_ADDRESS 268 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 269 #endif 270 271 #ifndef CONFIG_SYS_MONITOR_BASE 272 #ifdef CONFIG_SPL_BUILD 273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 274 #else 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 276 #endif 277 #endif 278 279 /* High Level Configuration Options */ 280 #define CONFIG_BOOKE 281 #define CONFIG_E500 282 283 #define CONFIG_MP 284 285 #define CONFIG_FSL_ELBC 286 #define CONFIG_PCI 287 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 288 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 289 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 290 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 291 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 292 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 293 294 #define CONFIG_FSL_LAW 295 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 296 #define CONFIG_ENV_OVERWRITE 297 298 #define CONFIG_CMD_SATA 299 #define CONFIG_SATA_SIL 300 #define CONFIG_SYS_SATA_MAX_DEVICE 2 301 #define CONFIG_LIBATA 302 #define CONFIG_LBA48 303 304 #if defined(CONFIG_P2020RDB) 305 #define CONFIG_SYS_CLK_FREQ 100000000 306 #else 307 #define CONFIG_SYS_CLK_FREQ 66666666 308 #endif 309 #define CONFIG_DDR_CLK_FREQ 66666666 310 311 #define CONFIG_HWCONFIG 312 /* 313 * These can be toggled for performance analysis, otherwise use default. 314 */ 315 #define CONFIG_L2_CACHE 316 #define CONFIG_BTB 317 318 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 319 320 #define CONFIG_ENABLE_36BIT_PHYS 321 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_ADDR_MAP 1 324 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 325 #endif 326 327 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 328 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 329 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 330 331 #define CONFIG_SYS_CCSRBAR 0xffe00000 332 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 333 334 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 335 SPL code*/ 336 #ifdef CONFIG_SPL_BUILD 337 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 338 #endif 339 340 /* DDR Setup */ 341 #define CONFIG_SYS_FSL_DDR3 342 #define CONFIG_SYS_DDR_RAW_TIMING 343 #define CONFIG_DDR_SPD 344 #define CONFIG_SYS_SPD_BUS_NUM 1 345 #define SPD_EEPROM_ADDRESS 0x52 346 #undef CONFIG_FSL_DDR_INTERACTIVE 347 348 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 349 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 350 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 351 #else 352 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 353 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 354 #endif 355 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 356 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 357 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 358 359 #define CONFIG_NUM_DDR_CONTROLLERS 1 360 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 361 362 /* Default settings for DDR3 */ 363 #ifndef CONFIG_P2020RDB 364 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 365 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 366 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 367 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 368 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 369 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 370 371 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 372 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 373 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 374 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 375 376 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 377 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 378 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 379 #define CONFIG_SYS_DDR_RCW_1 0x00000000 380 #define CONFIG_SYS_DDR_RCW_2 0x00000000 381 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 382 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 383 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 384 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 385 386 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 387 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 388 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 389 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 390 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 391 #define CONFIG_SYS_DDR_MODE_1 0x40461520 392 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 393 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 394 #endif 395 396 #undef CONFIG_CLOCKS_IN_MHZ 397 398 /* 399 * Memory map 400 * 401 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 402 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 403 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 404 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 405 * (early boot only) 406 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 407 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 408 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 409 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 410 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 411 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 412 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 413 */ 414 415 /* 416 * Local Bus Definitions 417 */ 418 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 419 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 420 #define CONFIG_SYS_FLASH_BASE 0xec000000 421 #elif defined(CONFIG_P1020UTM) 422 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 423 #define CONFIG_SYS_FLASH_BASE 0xee000000 424 #else 425 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 426 #define CONFIG_SYS_FLASH_BASE 0xef000000 427 #endif 428 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 431 #else 432 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 433 #endif 434 435 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 436 | BR_PS_16 | BR_V) 437 438 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 439 440 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 441 #define CONFIG_SYS_FLASH_QUIET_TEST 442 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 443 444 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 445 446 #undef CONFIG_SYS_FLASH_CHECKSUM 447 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 448 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 449 450 #define CONFIG_FLASH_CFI_DRIVER 451 #define CONFIG_SYS_FLASH_CFI 452 #define CONFIG_SYS_FLASH_EMPTY_INFO 453 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 454 455 /* Nand Flash */ 456 #ifdef CONFIG_NAND_FSL_ELBC 457 #define CONFIG_SYS_NAND_BASE 0xff800000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 460 #else 461 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 462 #endif 463 464 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 465 #define CONFIG_SYS_MAX_NAND_DEVICE 1 466 #define CONFIG_CMD_NAND 467 #if defined(CONFIG_P1020RDB_PD) 468 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 469 #else 470 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 471 #endif 472 473 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 474 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 475 | BR_PS_8 /* Port Size = 8 bit */ \ 476 | BR_MS_FCM /* MSEL = FCM */ \ 477 | BR_V) /* valid */ 478 #if defined(CONFIG_P1020RDB_PD) 479 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 480 | OR_FCM_PGS /* Large Page*/ \ 481 | OR_FCM_CSCT \ 482 | OR_FCM_CST \ 483 | OR_FCM_CHT \ 484 | OR_FCM_SCY_1 \ 485 | OR_FCM_TRLX \ 486 | OR_FCM_EHTR) 487 #else 488 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 489 | OR_FCM_CSCT \ 490 | OR_FCM_CST \ 491 | OR_FCM_CHT \ 492 | OR_FCM_SCY_1 \ 493 | OR_FCM_TRLX \ 494 | OR_FCM_EHTR) 495 #endif 496 #endif /* CONFIG_NAND_FSL_ELBC */ 497 498 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 499 500 #define CONFIG_SYS_INIT_RAM_LOCK 501 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 504 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 505 /* The assembler doesn't like typecast */ 506 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 507 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 508 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 509 #else 510 /* Initial L1 address */ 511 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 512 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 513 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 514 #endif 515 /* Size of used area in RAM */ 516 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 517 518 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 519 GENERATED_GBL_DATA_SIZE) 520 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 521 522 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 523 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 524 525 #define CONFIG_SYS_CPLD_BASE 0xffa00000 526 #ifdef CONFIG_PHYS_64BIT 527 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 528 #else 529 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 530 #endif 531 /* CPLD config size: 1Mb */ 532 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 533 BR_PS_8 | BR_V) 534 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 535 536 #define CONFIG_SYS_PMC_BASE 0xff980000 537 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 538 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 539 BR_PS_8 | BR_V) 540 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 541 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 542 OR_GPCM_EAD) 543 544 #ifdef CONFIG_NAND 545 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 546 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 547 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 548 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 549 #else 550 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 551 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 552 #ifdef CONFIG_NAND_FSL_ELBC 553 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 554 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 555 #endif 556 #endif 557 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 558 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 559 560 /* Vsc7385 switch */ 561 #ifdef CONFIG_VSC7385_ENET 562 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 563 564 #ifdef CONFIG_PHYS_64BIT 565 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 566 #else 567 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 568 #endif 569 570 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 571 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 572 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 573 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 574 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 575 576 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 577 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 578 579 /* The size of the VSC7385 firmware image */ 580 #define CONFIG_VSC7385_IMAGE_SIZE 8192 581 #endif 582 583 /* 584 * Config the L2 Cache as L2 SRAM 585 */ 586 #if defined(CONFIG_SPL_BUILD) 587 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 588 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 589 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 590 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 591 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 592 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 593 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 594 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 595 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 596 #if defined(CONFIG_P2020RDB) 597 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 598 #else 599 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 600 #endif 601 #elif defined(CONFIG_NAND) 602 #ifdef CONFIG_TPL_BUILD 603 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 604 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 605 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 606 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 607 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 608 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 609 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 610 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 611 #else 612 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 613 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 614 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 615 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 616 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 617 #endif /* CONFIG_TPL_BUILD */ 618 #endif 619 #endif 620 621 /* Serial Port - controlled on board with jumper J8 622 * open - index 2 623 * shorted - index 1 624 */ 625 #define CONFIG_CONS_INDEX 1 626 #undef CONFIG_SERIAL_SOFTWARE_FIFO 627 #define CONFIG_SYS_NS16550_SERIAL 628 #define CONFIG_SYS_NS16550_REG_SIZE 1 629 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 630 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 631 #define CONFIG_NS16550_MIN_FUNCTIONS 632 #endif 633 634 #define CONFIG_SYS_BAUDRATE_TABLE \ 635 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 636 637 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 638 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 639 640 /* I2C */ 641 #define CONFIG_SYS_I2C 642 #define CONFIG_SYS_I2C_FSL 643 #define CONFIG_SYS_FSL_I2C_SPEED 400000 644 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 645 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 646 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 647 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 648 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 649 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 650 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 651 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 652 653 /* 654 * I2C2 EEPROM 655 */ 656 #undef CONFIG_ID_EEPROM 657 658 #define CONFIG_RTC_PT7C4338 659 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 660 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 661 662 /* enable read and write access to EEPROM */ 663 #define CONFIG_CMD_EEPROM 664 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 665 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 666 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 667 668 /* 669 * eSPI - Enhanced SPI 670 */ 671 #define CONFIG_HARD_SPI 672 673 #if defined(CONFIG_SPI_FLASH) 674 #define CONFIG_SF_DEFAULT_SPEED 10000000 675 #define CONFIG_SF_DEFAULT_MODE 0 676 #endif 677 678 #if defined(CONFIG_PCI) 679 /* 680 * General PCI 681 * Memory space is mapped 1-1, but I/O space must start from 0. 682 */ 683 684 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 685 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 686 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 687 #ifdef CONFIG_PHYS_64BIT 688 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 689 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 690 #else 691 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 692 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 693 #endif 694 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 695 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 696 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 697 #ifdef CONFIG_PHYS_64BIT 698 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 699 #else 700 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 701 #endif 702 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 703 704 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 705 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 706 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 707 #ifdef CONFIG_PHYS_64BIT 708 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 709 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 710 #else 711 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 712 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 713 #endif 714 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 715 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 716 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 717 #ifdef CONFIG_PHYS_64BIT 718 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 719 #else 720 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 721 #endif 722 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 723 724 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 725 #define CONFIG_CMD_PCI 726 727 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 728 #define CONFIG_DOS_PARTITION 729 #endif /* CONFIG_PCI */ 730 731 #if defined(CONFIG_TSEC_ENET) 732 #define CONFIG_MII /* MII PHY management */ 733 #define CONFIG_TSEC1 734 #define CONFIG_TSEC1_NAME "eTSEC1" 735 #define CONFIG_TSEC2 736 #define CONFIG_TSEC2_NAME "eTSEC2" 737 #define CONFIG_TSEC3 738 #define CONFIG_TSEC3_NAME "eTSEC3" 739 740 #define TSEC1_PHY_ADDR 2 741 #define TSEC2_PHY_ADDR 0 742 #define TSEC3_PHY_ADDR 1 743 744 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 745 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 746 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 747 748 #define TSEC1_PHYIDX 0 749 #define TSEC2_PHYIDX 0 750 #define TSEC3_PHYIDX 0 751 752 #define CONFIG_ETHPRIME "eTSEC1" 753 754 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 755 756 #define CONFIG_HAS_ETH0 757 #define CONFIG_HAS_ETH1 758 #define CONFIG_HAS_ETH2 759 #endif /* CONFIG_TSEC_ENET */ 760 761 #ifdef CONFIG_QE 762 /* QE microcode/firmware address */ 763 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 764 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 765 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 766 #endif /* CONFIG_QE */ 767 768 #ifdef CONFIG_P1025RDB 769 /* 770 * QE UEC ethernet configuration 771 */ 772 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 773 774 #undef CONFIG_UEC_ETH 775 #define CONFIG_PHY_MODE_NEED_CHANGE 776 777 #define CONFIG_UEC_ETH1 /* ETH1 */ 778 #define CONFIG_HAS_ETH0 779 780 #ifdef CONFIG_UEC_ETH1 781 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 782 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 783 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 784 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 785 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 786 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 787 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 788 #endif /* CONFIG_UEC_ETH1 */ 789 790 #define CONFIG_UEC_ETH5 /* ETH5 */ 791 #define CONFIG_HAS_ETH1 792 793 #ifdef CONFIG_UEC_ETH5 794 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 795 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 796 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 797 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 798 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 799 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 800 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 801 #endif /* CONFIG_UEC_ETH5 */ 802 #endif /* CONFIG_P1025RDB */ 803 804 /* 805 * Environment 806 */ 807 #ifdef CONFIG_SPIFLASH 808 #define CONFIG_ENV_IS_IN_SPI_FLASH 809 #define CONFIG_ENV_SPI_BUS 0 810 #define CONFIG_ENV_SPI_CS 0 811 #define CONFIG_ENV_SPI_MAX_HZ 10000000 812 #define CONFIG_ENV_SPI_MODE 0 813 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 814 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 815 #define CONFIG_ENV_SECT_SIZE 0x10000 816 #elif defined(CONFIG_SDCARD) 817 #define CONFIG_ENV_IS_IN_MMC 818 #define CONFIG_FSL_FIXED_MMC_LOCATION 819 #define CONFIG_ENV_SIZE 0x2000 820 #define CONFIG_SYS_MMC_ENV_DEV 0 821 #elif defined(CONFIG_NAND) 822 #ifdef CONFIG_TPL_BUILD 823 #define CONFIG_ENV_SIZE 0x2000 824 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 825 #else 826 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 827 #endif 828 #define CONFIG_ENV_IS_IN_NAND 829 #define CONFIG_ENV_OFFSET (1024 * 1024) 830 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 831 #elif defined(CONFIG_SYS_RAMBOOT) 832 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 833 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 834 #define CONFIG_ENV_SIZE 0x2000 835 #else 836 #define CONFIG_ENV_IS_IN_FLASH 837 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 838 #define CONFIG_ENV_SIZE 0x2000 839 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 840 #endif 841 842 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 843 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 844 845 /* 846 * Command line configuration. 847 */ 848 #define CONFIG_CMD_IRQ 849 #define CONFIG_CMD_DATE 850 #define CONFIG_CMD_REGINFO 851 852 /* 853 * USB 854 */ 855 #define CONFIG_HAS_FSL_DR_USB 856 857 #if defined(CONFIG_HAS_FSL_DR_USB) 858 #define CONFIG_USB_EHCI 859 860 #ifdef CONFIG_USB_EHCI 861 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 862 #define CONFIG_USB_EHCI_FSL 863 #endif 864 #endif 865 866 #if defined(CONFIG_P1020RDB_PD) 867 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 868 #endif 869 870 #define CONFIG_MMC 871 872 #ifdef CONFIG_MMC 873 #define CONFIG_FSL_ESDHC 874 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 875 #define CONFIG_GENERIC_MMC 876 #endif 877 878 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 879 || defined(CONFIG_FSL_SATA) 880 #define CONFIG_DOS_PARTITION 881 #endif 882 883 #undef CONFIG_WATCHDOG /* watchdog disabled */ 884 885 /* 886 * Miscellaneous configurable options 887 */ 888 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 889 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 890 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 891 #if defined(CONFIG_CMD_KGDB) 892 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 893 #else 894 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 895 #endif 896 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 897 /* Print Buffer Size */ 898 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 899 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 900 901 /* 902 * For booting Linux, the board info and command line data 903 * have to be in the first 64 MB of memory, since this is 904 * the maximum mapped by the Linux kernel during initialization. 905 */ 906 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 907 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 908 909 #if defined(CONFIG_CMD_KGDB) 910 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 911 #endif 912 913 /* 914 * Environment Configuration 915 */ 916 #define CONFIG_HOSTNAME unknown 917 #define CONFIG_ROOTPATH "/opt/nfsroot" 918 #define CONFIG_BOOTFILE "uImage" 919 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 920 921 /* default location for tftp and bootm */ 922 #define CONFIG_LOADADDR 1000000 923 924 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 925 926 #define CONFIG_BAUDRATE 115200 927 928 #ifdef __SW_BOOT_NOR 929 #define __NOR_RST_CMD \ 930 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 931 i2c mw 18 3 __SW_BOOT_MASK 1; reset 932 #endif 933 #ifdef __SW_BOOT_SPI 934 #define __SPI_RST_CMD \ 935 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 936 i2c mw 18 3 __SW_BOOT_MASK 1; reset 937 #endif 938 #ifdef __SW_BOOT_SD 939 #define __SD_RST_CMD \ 940 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 941 i2c mw 18 3 __SW_BOOT_MASK 1; reset 942 #endif 943 #ifdef __SW_BOOT_NAND 944 #define __NAND_RST_CMD \ 945 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 946 i2c mw 18 3 __SW_BOOT_MASK 1; reset 947 #endif 948 #ifdef __SW_BOOT_PCIE 949 #define __PCIE_RST_CMD \ 950 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 951 i2c mw 18 3 __SW_BOOT_MASK 1; reset 952 #endif 953 954 #define CONFIG_EXTRA_ENV_SETTINGS \ 955 "netdev=eth0\0" \ 956 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 957 "loadaddr=1000000\0" \ 958 "bootfile=uImage\0" \ 959 "tftpflash=tftpboot $loadaddr $uboot; " \ 960 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 961 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 962 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 963 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 964 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 965 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 966 "consoledev=ttyS0\0" \ 967 "ramdiskaddr=2000000\0" \ 968 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 969 "fdtaddr=1e00000\0" \ 970 "bdev=sda1\0" \ 971 "jffs2nor=mtdblock3\0" \ 972 "norbootaddr=ef080000\0" \ 973 "norfdtaddr=ef040000\0" \ 974 "jffs2nand=mtdblock9\0" \ 975 "nandbootaddr=100000\0" \ 976 "nandfdtaddr=80000\0" \ 977 "ramdisk_size=120000\0" \ 978 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 979 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 980 __stringify(__NOR_RST_CMD)"\0" \ 981 __stringify(__SPI_RST_CMD)"\0" \ 982 __stringify(__SD_RST_CMD)"\0" \ 983 __stringify(__NAND_RST_CMD)"\0" \ 984 __stringify(__PCIE_RST_CMD)"\0" 985 986 #define CONFIG_NFSBOOTCOMMAND \ 987 "setenv bootargs root=/dev/nfs rw " \ 988 "nfsroot=$serverip:$rootpath " \ 989 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 990 "console=$consoledev,$baudrate $othbootargs;" \ 991 "tftp $loadaddr $bootfile;" \ 992 "tftp $fdtaddr $fdtfile;" \ 993 "bootm $loadaddr - $fdtaddr" 994 995 #define CONFIG_HDBOOT \ 996 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 997 "console=$consoledev,$baudrate $othbootargs;" \ 998 "usb start;" \ 999 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1000 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1001 "bootm $loadaddr - $fdtaddr" 1002 1003 #define CONFIG_USB_FAT_BOOT \ 1004 "setenv bootargs root=/dev/ram rw " \ 1005 "console=$consoledev,$baudrate $othbootargs " \ 1006 "ramdisk_size=$ramdisk_size;" \ 1007 "usb start;" \ 1008 "fatload usb 0:2 $loadaddr $bootfile;" \ 1009 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1010 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1011 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1012 1013 #define CONFIG_USB_EXT2_BOOT \ 1014 "setenv bootargs root=/dev/ram rw " \ 1015 "console=$consoledev,$baudrate $othbootargs " \ 1016 "ramdisk_size=$ramdisk_size;" \ 1017 "usb start;" \ 1018 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1019 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1020 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1021 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1022 1023 #define CONFIG_NORBOOT \ 1024 "setenv bootargs root=/dev/$jffs2nor rw " \ 1025 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1026 "bootm $norbootaddr - $norfdtaddr" 1027 1028 #define CONFIG_RAMBOOTCOMMAND \ 1029 "setenv bootargs root=/dev/ram rw " \ 1030 "console=$consoledev,$baudrate $othbootargs " \ 1031 "ramdisk_size=$ramdisk_size;" \ 1032 "tftp $ramdiskaddr $ramdiskfile;" \ 1033 "tftp $loadaddr $bootfile;" \ 1034 "tftp $fdtaddr $fdtfile;" \ 1035 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1036 1037 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1038 1039 #endif /* __CONFIG_H */ 1040