1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MMC_MINIMAL 18 #define CONFIG_SPL_FLUSH_IMAGE 19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 20 #define CONFIG_FSL_LAW /* Use common FSL init code */ 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 23 #define CONFIG_SPL_PAD_TO 0x20000 24 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #define CONFIG_SPL_SPI_SUPPORT 39 #define CONFIG_SPL_SPI_FLASH_SUPPORT 40 #define CONFIG_SPL_SPI_FLASH_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_FSL_LAW /* Use common FSL init code */ 44 #define CONFIG_SYS_TEXT_BASE 0x11001000 45 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 46 #define CONFIG_SPL_PAD_TO 0x20000 47 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 54 #define CONFIG_SPL_SPI_BOOT 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_COMMON_INIT_DDR 57 #endif 58 #endif 59 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 62 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 63 64 #ifdef CONFIG_NAND 65 #ifdef CONFIG_TPL_BUILD 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_NAND_INIT 69 #define CONFIG_SPL_COMMON_INIT_DDR 70 #define CONFIG_SPL_MAX_SIZE (128 << 10) 71 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 75 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 77 #elif defined(CONFIG_SPL_BUILD) 78 #define CONFIG_SPL_INIT_MINIMAL 79 #define CONFIG_SPL_FLUSH_IMAGE 80 #define CONFIG_SPL_TEXT_BASE 0xff800000 81 #define CONFIG_SPL_MAX_SIZE 4096 82 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 83 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 84 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 85 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 86 #endif 87 #define CONFIG_SPL_PAD_TO 0x20000 88 #define CONFIG_TPL_PAD_TO 0x20000 89 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 90 #define CONFIG_SYS_TEXT_BASE 0x11001000 91 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 92 #endif 93 94 /* High Level Configuration Options */ 95 #define CONFIG_BOOKE /* BOOKE */ 96 #define CONFIG_E500 /* BOOKE e500 family */ 97 #define CONFIG_P1022 98 #define CONFIG_P1022DS 99 #define CONFIG_MP /* support multiple processors */ 100 101 #ifndef CONFIG_SYS_TEXT_BASE 102 #define CONFIG_SYS_TEXT_BASE 0xeff40000 103 #endif 104 105 #ifndef CONFIG_RESET_VECTOR_ADDRESS 106 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 107 #endif 108 109 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 110 #define CONFIG_PCI /* Enable PCI/PCIE */ 111 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 112 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 113 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 114 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 115 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 116 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 117 118 #define CONFIG_ENABLE_36BIT_PHYS 119 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_ADDR_MAP 122 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 123 #endif 124 125 #define CONFIG_FSL_LAW /* Use common FSL init code */ 126 127 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 128 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 129 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_L2_CACHE 135 #define CONFIG_BTB 136 137 #define CONFIG_SYS_MEMTEST_START 0x00000000 138 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 139 140 #define CONFIG_SYS_CCSRBAR 0xffe00000 141 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 142 143 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 144 SPL code*/ 145 #ifdef CONFIG_SPL_BUILD 146 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 147 #endif 148 149 /* DDR Setup */ 150 #define CONFIG_DDR_SPD 151 #define CONFIG_VERY_BIG_RAM 152 #define CONFIG_SYS_FSL_DDR3 153 154 #ifdef CONFIG_DDR_ECC 155 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 156 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 157 #endif 158 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 161 162 #define CONFIG_NUM_DDR_CONTROLLERS 1 163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 164 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 165 166 /* I2C addresses of SPD EEPROMs */ 167 #define CONFIG_SYS_SPD_BUS_NUM 1 168 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 169 170 /* These are used when DDR doesn't use SPD. */ 171 #define CONFIG_SYS_SDRAM_SIZE 2048 172 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 173 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 174 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 175 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 176 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 177 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 178 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 179 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 180 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 181 #define CONFIG_SYS_DDR_MODE_1 0x00441221 182 #define CONFIG_SYS_DDR_MODE_2 0x00000000 183 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 184 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 185 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 186 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 187 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 188 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 189 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 190 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 191 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 192 193 /* 194 * Memory map 195 * 196 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 197 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 198 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 199 * 200 * Localbus cacheable (TBD) 201 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 202 * 203 * Localbus non-cacheable 204 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 205 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 206 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 207 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 208 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 209 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 210 */ 211 212 /* 213 * Local Bus Definitions 214 */ 215 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 216 #ifdef CONFIG_PHYS_64BIT 217 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 218 #else 219 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 220 #endif 221 222 #define CONFIG_FLASH_BR_PRELIM \ 223 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 224 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 225 226 #ifdef CONFIG_NAND 227 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 228 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 229 #else 230 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 231 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 232 #endif 233 234 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 240 241 #ifndef CONFIG_SYS_MONITOR_BASE 242 #ifdef CONFIG_SPL_BUILD 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 244 #else 245 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 246 #endif 247 #endif 248 249 #define CONFIG_FLASH_CFI_DRIVER 250 #define CONFIG_SYS_FLASH_CFI 251 #define CONFIG_SYS_FLASH_EMPTY_INFO 252 253 /* Nand Flash */ 254 #if defined(CONFIG_NAND_FSL_ELBC) 255 #define CONFIG_SYS_NAND_BASE 0xff800000 256 #ifdef CONFIG_PHYS_64BIT 257 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 258 #else 259 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 260 #endif 261 262 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 263 #define CONFIG_SYS_MAX_NAND_DEVICE 1 264 #define CONFIG_CMD_NAND 1 265 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 266 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 267 268 /* NAND flash config */ 269 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 270 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 271 | BR_PS_8 /* Port Size = 8 bit */ \ 272 | BR_MS_FCM /* MSEL = FCM */ \ 273 | BR_V) /* valid */ 274 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 275 | OR_FCM_PGS /* Large Page*/ \ 276 | OR_FCM_CSCT \ 277 | OR_FCM_CST \ 278 | OR_FCM_CHT \ 279 | OR_FCM_SCY_1 \ 280 | OR_FCM_TRLX \ 281 | OR_FCM_EHTR) 282 #ifdef CONFIG_NAND 283 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 284 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 285 #else 286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 288 #endif 289 290 #endif /* CONFIG_NAND_FSL_ELBC */ 291 292 #define CONFIG_BOARD_EARLY_INIT_F 293 #define CONFIG_BOARD_EARLY_INIT_R 294 #define CONFIG_MISC_INIT_R 295 #define CONFIG_HWCONFIG 296 297 #define CONFIG_FSL_NGPIXIS 298 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 299 #ifdef CONFIG_PHYS_64BIT 300 #define PIXIS_BASE_PHYS 0xfffdf0000ull 301 #else 302 #define PIXIS_BASE_PHYS PIXIS_BASE 303 #endif 304 305 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 306 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 307 308 #define PIXIS_LBMAP_SWITCH 7 309 #define PIXIS_LBMAP_MASK 0xF0 310 #define PIXIS_LBMAP_ALTBANK 0x20 311 #define PIXIS_SPD 0x07 312 #define PIXIS_SPD_SYSCLK_MASK 0x07 313 #define PIXIS_ELBC_SPI_MASK 0xc0 314 #define PIXIS_SPI 0x80 315 316 #define CONFIG_SYS_INIT_RAM_LOCK 317 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 318 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 319 320 #define CONFIG_SYS_GBL_DATA_OFFSET \ 321 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 322 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 323 324 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 325 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 326 327 /* 328 * Config the L2 Cache as L2 SRAM 329 */ 330 #if defined(CONFIG_SPL_BUILD) 331 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 332 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 333 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 334 #define CONFIG_SYS_L2_SIZE (256 << 10) 335 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 336 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 337 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 338 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 339 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 340 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 341 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 342 #elif defined(CONFIG_NAND) 343 #ifdef CONFIG_TPL_BUILD 344 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 345 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 346 #define CONFIG_SYS_L2_SIZE (256 << 10) 347 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 348 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 349 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 350 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 351 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 352 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 353 #else 354 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 355 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 356 #define CONFIG_SYS_L2_SIZE (256 << 10) 357 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 358 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 359 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 360 #endif 361 #endif 362 #endif 363 364 /* 365 * Serial Port 366 */ 367 #define CONFIG_CONS_INDEX 1 368 #define CONFIG_SYS_NS16550_SERIAL 369 #define CONFIG_SYS_NS16550_REG_SIZE 1 370 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 371 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 372 #define CONFIG_NS16550_MIN_FUNCTIONS 373 #endif 374 375 #define CONFIG_SYS_BAUDRATE_TABLE \ 376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 377 378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 380 381 /* Video */ 382 383 #ifdef CONFIG_FSL_DIU_FB 384 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 385 #define CONFIG_VIDEO 386 #define CONFIG_CMD_BMP 387 #define CONFIG_CFB_CONSOLE 388 #define CONFIG_VIDEO_SW_CURSOR 389 #define CONFIG_VGA_AS_SINGLE_DEVICE 390 #define CONFIG_VIDEO_LOGO 391 #define CONFIG_VIDEO_BMP_LOGO 392 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 393 /* 394 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 395 * disable empty flash sector detection, which is I/O-intensive. 396 */ 397 #undef CONFIG_SYS_FLASH_EMPTY_INFO 398 #endif 399 400 #ifndef CONFIG_FSL_DIU_FB 401 #endif 402 403 #ifdef CONFIG_ATI 404 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 405 #define CONFIG_VIDEO 406 #define CONFIG_BIOSEMU 407 #define CONFIG_VIDEO_SW_CURSOR 408 #define CONFIG_ATI_RADEON_FB 409 #define CONFIG_VIDEO_LOGO 410 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 411 #define CONFIG_CFB_CONSOLE 412 #define CONFIG_VGA_AS_SINGLE_DEVICE 413 #endif 414 415 /* I2C */ 416 #define CONFIG_SYS_I2C 417 #define CONFIG_SYS_I2C_FSL 418 #define CONFIG_SYS_FSL_I2C_SPEED 400000 419 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 421 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 422 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 424 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 425 426 /* 427 * I2C2 EEPROM 428 */ 429 #define CONFIG_ID_EEPROM 430 #define CONFIG_SYS_I2C_EEPROM_NXID 431 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 432 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 433 #define CONFIG_SYS_EEPROM_BUS_NUM 1 434 435 /* 436 * eSPI - Enhanced SPI 437 */ 438 439 #define CONFIG_HARD_SPI 440 441 #define CONFIG_SF_DEFAULT_SPEED 10000000 442 #define CONFIG_SF_DEFAULT_MODE 0 443 444 /* 445 * General PCI 446 * Memory space is mapped 1-1, but I/O space must start from 0. 447 */ 448 449 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 450 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 454 #else 455 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 456 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 457 #endif 458 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 459 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 460 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 463 #else 464 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 465 #endif 466 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 467 468 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 472 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 473 #else 474 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 475 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 476 #endif 477 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 479 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 482 #else 483 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 484 #endif 485 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 486 487 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 488 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 492 #else 493 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 494 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 495 #endif 496 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 497 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 498 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 501 #else 502 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 503 #endif 504 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 505 506 #ifdef CONFIG_PCI 507 #define CONFIG_PCI_INDIRECT_BRIDGE 508 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 509 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 510 #endif 511 512 /* SATA */ 513 #define CONFIG_LIBATA 514 #define CONFIG_FSL_SATA 515 #define CONFIG_FSL_SATA_V2 516 517 #define CONFIG_SYS_SATA_MAX_DEVICE 2 518 #define CONFIG_SATA1 519 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 520 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 521 #define CONFIG_SATA2 522 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 523 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 524 525 #ifdef CONFIG_FSL_SATA 526 #define CONFIG_LBA48 527 #define CONFIG_CMD_SATA 528 #define CONFIG_DOS_PARTITION 529 #endif 530 531 #define CONFIG_MMC 532 #ifdef CONFIG_MMC 533 #define CONFIG_FSL_ESDHC 534 #define CONFIG_GENERIC_MMC 535 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 536 #endif 537 538 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 539 #define CONFIG_DOS_PARTITION 540 #endif 541 542 #define CONFIG_TSEC_ENET 543 #ifdef CONFIG_TSEC_ENET 544 545 #define CONFIG_TSECV2 546 547 #define CONFIG_MII /* MII PHY management */ 548 #define CONFIG_TSEC1 1 549 #define CONFIG_TSEC1_NAME "eTSEC1" 550 #define CONFIG_TSEC2 1 551 #define CONFIG_TSEC2_NAME "eTSEC2" 552 553 #define TSEC1_PHY_ADDR 1 554 #define TSEC2_PHY_ADDR 2 555 556 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 557 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 558 559 #define TSEC1_PHYIDX 0 560 #define TSEC2_PHYIDX 0 561 562 #define CONFIG_ETHPRIME "eTSEC1" 563 564 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 565 #endif 566 567 /* 568 * Dynamic MTD Partition support with mtdparts 569 */ 570 #define CONFIG_MTD_DEVICE 571 #define CONFIG_MTD_PARTITIONS 572 #define CONFIG_CMD_MTDPARTS 573 #define CONFIG_FLASH_CFI_MTD 574 #ifdef CONFIG_PHYS_64BIT 575 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 576 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 577 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 578 "512k(dtb),768k(u-boot)" 579 #else 580 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 581 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 582 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 583 "512k(dtb),768k(u-boot)" 584 #endif 585 586 /* 587 * Environment 588 */ 589 #ifdef CONFIG_SPIFLASH 590 #define CONFIG_ENV_IS_IN_SPI_FLASH 591 #define CONFIG_ENV_SPI_BUS 0 592 #define CONFIG_ENV_SPI_CS 0 593 #define CONFIG_ENV_SPI_MAX_HZ 10000000 594 #define CONFIG_ENV_SPI_MODE 0 595 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 596 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 597 #define CONFIG_ENV_SECT_SIZE 0x10000 598 #elif defined(CONFIG_SDCARD) 599 #define CONFIG_ENV_IS_IN_MMC 600 #define CONFIG_FSL_FIXED_MMC_LOCATION 601 #define CONFIG_ENV_SIZE 0x2000 602 #define CONFIG_SYS_MMC_ENV_DEV 0 603 #elif defined(CONFIG_NAND) 604 #ifdef CONFIG_TPL_BUILD 605 #define CONFIG_ENV_SIZE 0x2000 606 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 607 #else 608 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 609 #endif 610 #define CONFIG_ENV_IS_IN_NAND 611 #define CONFIG_ENV_OFFSET (1024 * 1024) 612 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 613 #elif defined(CONFIG_SYS_RAMBOOT) 614 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 615 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 616 #define CONFIG_ENV_SIZE 0x2000 617 #else 618 #define CONFIG_ENV_IS_IN_FLASH 619 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 620 #define CONFIG_ENV_SIZE 0x2000 621 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 622 #endif 623 624 #define CONFIG_LOADS_ECHO 625 #define CONFIG_SYS_LOADS_BAUD_CHANGE 626 627 /* 628 * Command line configuration. 629 */ 630 #define CONFIG_CMD_ERRATA 631 #define CONFIG_CMD_IRQ 632 #define CONFIG_CMD_REGINFO 633 634 #ifdef CONFIG_PCI 635 #define CONFIG_CMD_PCI 636 #endif 637 638 /* 639 * USB 640 */ 641 #define CONFIG_HAS_FSL_DR_USB 642 #ifdef CONFIG_HAS_FSL_DR_USB 643 #define CONFIG_USB_EHCI 644 645 #ifdef CONFIG_USB_EHCI 646 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 647 #define CONFIG_USB_EHCI_FSL 648 #endif 649 #endif 650 651 /* 652 * Miscellaneous configurable options 653 */ 654 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 655 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 656 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 657 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 658 #ifdef CONFIG_CMD_KGDB 659 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 660 #else 661 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 662 #endif 663 /* Print Buffer Size */ 664 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 665 #define CONFIG_SYS_MAXARGS 16 666 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 667 668 /* 669 * For booting Linux, the board info and command line data 670 * have to be in the first 64 MB of memory, since this is 671 * the maximum mapped by the Linux kernel during initialization. 672 */ 673 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 674 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 675 676 #ifdef CONFIG_CMD_KGDB 677 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 678 #endif 679 680 /* 681 * Environment Configuration 682 */ 683 684 #define CONFIG_HOSTNAME p1022ds 685 #define CONFIG_ROOTPATH "/opt/nfsroot" 686 #define CONFIG_BOOTFILE "uImage" 687 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 688 689 #define CONFIG_LOADADDR 1000000 690 691 692 #define CONFIG_BAUDRATE 115200 693 694 #define CONFIG_EXTRA_ENV_SETTINGS \ 695 "netdev=eth0\0" \ 696 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 697 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 698 "tftpflash=tftpboot $loadaddr $uboot && " \ 699 "protect off $ubootaddr +$filesize && " \ 700 "erase $ubootaddr +$filesize && " \ 701 "cp.b $loadaddr $ubootaddr $filesize && " \ 702 "protect on $ubootaddr +$filesize && " \ 703 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 704 "consoledev=ttyS0\0" \ 705 "ramdiskaddr=2000000\0" \ 706 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 707 "fdtaddr=1e00000\0" \ 708 "fdtfile=p1022ds.dtb\0" \ 709 "bdev=sda3\0" \ 710 "hwconfig=esdhc;audclk:12\0" 711 712 #define CONFIG_HDBOOT \ 713 "setenv bootargs root=/dev/$bdev rw " \ 714 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr - $fdtaddr" 718 719 #define CONFIG_NFSBOOTCOMMAND \ 720 "setenv bootargs root=/dev/nfs rw " \ 721 "nfsroot=$serverip:$rootpath " \ 722 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 723 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr - $fdtaddr" 727 728 #define CONFIG_RAMBOOTCOMMAND \ 729 "setenv bootargs root=/dev/ram rw " \ 730 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 731 "tftp $ramdiskaddr $ramdiskfile;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr $ramdiskaddr $fdtaddr" 735 736 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 737 738 #endif 739